Need help implementing two different delays on a falling edge

[Soski14]

Hi, I'm working on a project where I have to output some digital SPWM signals through a cRIO-9030 to drive a three-phase inverter.

I need to avoid overlapping between the high PWM and the low PWM (considering that the rise and fall time are not equal to zero, I've measured them already in the oscilloscope). I'm currently using the NI 9401 to output those signals.

My problem is that I haven't found a way to delay the rising edge of the low PWM after an specific amount of time has passed since the falling edge of the high PWM has occurred.

I'm developing my VI in the FPGA directly.

I'll attach an screenshot of my current VI.

Thanks in advance

[GerdW]

Hi Soski,

you can measure time on a FPGA target, too!

So:

1. On a falling edge of the "High" PWM you start a counter.

2. After the counter has reached the target time you can switch on the "Low" PWM…

In the end it's just counting loop iterations in the FPGA when you want to generate digital PWM output signals!

(Hint: draw those signals on a sheet of paper to develop the algorithm.)

[Soski14]

Hi GerdW, thank you for your kind answer.

Could you illustrate me on how to exactly build a counter directly onto the FPGA in LabView?

I'm a newbie with this software and I'm not used to Graphical Programming yet.

Thank you again and sorry for the trouble.

[GerdW]

Hi Soski,

this is a counter (countdown) I made for a special counter I needed once:

It counts rising edges using the compound node with the feedback node…

[Soski14]

Thank you again,

what does this case structure looks like when the condition is "false"?

[GerdW]

Hi Soski,

inputs and outputs are just connected by wires: valid := FALSE, count := count

The point is: to count pulses you need to detect pulse edges and you need to keep a register/buffer (like the indicator in my image or a shift register) to store the counter…