Need some help. cRIO 9056 disconnects after hours of VI running with no issues

[Nadweb]

One concern I have now after doing a lot of digging is that I have too many serial open and close vi's. Instead of opening visa, doing all the 340 communication, and then closing, I have different sub vi's for each command and each one opens and closes visa. They are ordered using a sequence structure with waits between each sub vi (command) so reads/writes aren't stepping on one another. I'm wondering now if this is my issue? Easily fixable if it is.

[RavensFan · Accepted solution]

I don't know what you mean by a "slice" of a DAQ or of a RIO.

But if you are opening and closing VISA serial ports constantly, that is just a bad idea.  Open at the beginning of the program, read/write inside the loop, close after the program is done.

You can also drive to close and reopen in the event you run into an error, but that should be rare.

A PC can easily keep multiple serial ports  open at once.  Meanwhile I'd be worried that opening and closing the same port thousands of times could lead to some memory issue that causes problems in the driver for that port.

[Nadweb]

My apologies, we just refer to them as slices, but what I mean is an NI-9870, I believe that is what we use for serial commands. I don't recall the one for voltage collection at this moment.

Yes I realize now that it is bad idea, when I was building the VI it didn't occur to me to do it differently. There is a little learn as you go happening.

What you said about memory issues makes a lot of sense. Seems like VISA is crashing, which explains why all the channels disappear when in get the error. Even in max it says no visa channels detected until I close everything and restart the RIO.

Another solution to try it sounds like.

Really appreciate the replies!

[RavensFan]

Ok.  The NI-9870 is a module.  4 channel serial port.  Whatever you used for voltage acquisition would be a voltage module.

The only time I've heard the term "slice" used in programming was when it related to how much FPGA resources were being using when compiling a BIT file.

Hopefully making the changes to minimize the opening and closing of the serial ports will solve your problem.

You originally said you were using a USB cable to connect the cRIO to your host PC.  While I know you can do that, I've never done it, or heard of it done very often.  I would consider using an ethernet cable between the cRIO and your host PC.

Good Luck!

[Nadweb]

This seemed to do the trick. I changed it so all my channels now have a single open and close and now I haven't had any issues with the visa channels failing or losing connection with the rio. 

Thanks for talking it through with me!

P.s. Although everything seems to be working well, do I need to wire my Visa configure/open to a shift register?  

[RavensFan]

It might not be necessary.

But it wouldn't hurt to put the purple wire on shift registers.  If ever need to do an close and open within the loop, perhaps as part of an error handling case structure, you will definitely need shift registers.