PXIe 5170R FPGA decimation options

[ToeCutter]

Hi,

Can someone confirm if the decimator available on the 5170R FPGA palette if configured for power-of-2 decimation, only in fact supports a decimation factor of 2^1? All the other options appear greyed to me, and I've tried various methods to get around it (put it in an untimed loop, put it in a lower clocked timed loop, change the input options) without success. The only other option I can think of (I need anti-aliasing, not supported by the integer decimation, and I can't fit enough fractional decimators on for my channel count) is to stack up a few 2^1 decimators in series, but it feels messy and I'm not sure if it's optimal in the numerical fidelity stakes.

Any ideas?

Thanks

[GeorgeAF]

Hi ToeCutter,

My Name is George and I work as an Applications Engineer for National Instruments. I’m sorry it has taken so long for someone to help you with your query but we’ve had a lot of requests recently. Is this still an active problem?

I’m afraid I am not overly familiar with the concept of decimation but I understand you are trying to use power-of-2 decimation to reduce the sampling rate of a signal being measured with a 5170 R series PXIe module via FPGA. You would like to increase the factor of the decimator to increase the amount the signal is cut down but cannot increase it above 1.

To help troubleshoot the problem there are a few questions I hope you can answer to help me fully understand the problem;

• Could you give me a little background information on what your application is and how your hardware is set up?
• Have you tried your potential solution of stacking 2^1 decimators? If so does this work despite not being fully optimised?
• Why can you not use integer decimation?

Whilst I wait for a reply I will continue to do my own research into the issue and I will let you know if I find any more useful information that may help you.

Regards,

George

[ToeCutter]

Hi George,

Thanks for the response.

-Setup- single 5170R card in a PXI-e chassis with built in controller. (This is for starters- I will extend to two cards later), The application is just a simple oscilloscope- basically the 2014 NI scope design library 'stream to host' example pretty much does what I want, but from my understanding does not perform anti-aliasing when decimating), which is no good to me.

-I haven't tried stacking 2^1s- I need a wide range of decimation factors so this solution will be large and unwieldy, if it can be made to compile at all.

-Integer decimation does not provide the required anti-alias filtering, and there are no suitable anti-alias filters available in the palette.

[GeorgeAF]

Hi ToeCutter,

Thanks for answering my questions. I’ve been researching your problem and I’m afraid I can confirm that the decimator for your hardware only supports power-of-2 decimation with a factor of 1 due to a limitation in the hardware. I suggest investigating a way to add an anti-aliasing filter to your code in combination with an integer decimator to make up for the integer decimators lack of built in anti-aliasing. If this does not work try to find a way to stack power-of-2 decimators in an efficient way that will compile as you initially suggested.

Regards,

George