RT VI execution timing control by waiting for the end of FPGA VI execution

[catalysthw]

Hello NI forum,

I'd like to get some advices about RT VI start timing control.

I'm using cRIO-9074, NI 9411 DI module and NI 9215 AI module.

Software versions are 2013 version.

Attached FPGA VI have a simple feedback function to acquire analog data based on counter from digital pulses.  (maximum frequency of digital pulse is about 30 kHz. FXP for analog data indicator is unsigned, 18bits and 4bits )

In the FPGA VI, 112 is the last counter value for acquiring data.  

There are some issues after the last counter value for data acquisition.

1) Transfer the acquired data(array) from FPGA to RT after 112 counter value.

2) One time execution of RT VI after getting the array from FPGA: Doing some calcualtion in RT VI by using the datat from FPGA

3) one time FPGA execution to acquire data.

Could you give me some advices? 

[GerdW]

Hi catalyst,

LabVIEW comes with a lot of example VIs (see example finder) AND example projects!

There are example projects explaining how to transfer data to/from FPGA. Did you examine them?

Your VI looks overly complicated. Why not keep the last 13 AI samples in an array/memory and "trigger" data transfer on puls #112? Seems easier than using 13 comparisons and shift registers…