Here you mean you can have host Vi FIFO SIZE as big as posiible.I have huge data upto 5mb.so what size of FIFO I should use.I think maximum host FIFO size is 1048581.So if I have data more than that I should keep this maximum size for FIFO?
Just to clarify I should pass all the data at the same time to HOST FIFO?and FPGA FIFO how to receive data one-by one to process it later on FPGA ??
I have attached images of the progress I have made.
My main problem here is I want data from computer(HOst Vi) to be used by FPGA for processing.Hence I nedd to communiacate data from host PVI to FPGA VI after this data gets to FPGA I want to do some operations on this data and get output.
