SubVI implicit timing inside a LabVIEW FPGA SCTL

[EricLM]

I have a question regarding the implicit timing of a subVI within a SCTL when LabVIEW translates to VHDL. Does the translate flatten all code within the SCTL effectively removing subVI boundaries, or does a subVI act like a single sequence frame around that code.

For example, if I have a block of code inside a subVI that is not connected to any input or output of the subVI, does it still wait for all subVI inputs to be satisfied to execute? I know the answer is normally yes, but I wondered if this was different inside a SCTL. If the answer is still yes, does removing implicit timing in the FPGA build spec effectively remove that enforcement for any block of code that is not wired directly?

I ask, because sometimes I wonder if the code inside a subVI that is part of the critical path of a loop may be simplifying the BD, but may be hurting the critical path timing because certain functions/gates are not executing as soon as they would if not inside a subVI.

[WillD · Accepted solution]

The SCTL flattens all the code inside it, removing all intermediary registers.

So, yes use SubVI to cleanup / duplicate code inside SCTLs.

[Dragis]

Since everything inside a SCL must execute in one cycle, dataflow ordering of operations is essentially only governed by the actual data connections. Any pure ordering constructs like frames, VI boundaries, etc. are for all practical purposes removed by the compiler.