Too many open FGPA references! Error -63198

[MaxJoseph]

Hi all,

I am using an FPGA (7965R with 5761 digitiser front module) to do some real time data analysis. I want to use all four channels of the digitiser and use DMA FIFOs to send four streams of data for each channel. 4x4=16 DMA FIFOs which squeaks in just under the limit of 16 available DMA FIFOs on this FPGA/chassis. I want to do all this programatically, using actors, on the RT.

I am using Advanced Session Resources (ASR) to pull out specific FIFOs from the the FGPA reference. I then use FIFO reads in parallel FIFO listener loops to read the FIFOs. My problem is that I quickly receive a -63198 error, which I have deduced is because I am trying to open too many FPGA references. Does the 'cast' in ASR result in the creation of a new reference? I will assume from here that it does...

I read that there is a hard limit of 16 open FPGA references. Since I have 16 already from just the dynamic reads of 16 FIFOs, and I will have a few more when created when I initialise the system and go about creating the dynamic references, I suspect my error is caused by hitting this limit.

Now, solutions:

I could create each reference immediately before the read and close it right after, but I have read that this would add a lot of overhead to my reads! Not ideal for code that I want to operate ASAP.  My host PC also has a FPGA reference for sending settings direct to the FPGA, in this case I could manage with opening and closing the reference each time, since I don't need the response to be deteministic or fast.

My only solution so far is to squeeze all four data streams for each channel into a single DMA FIFO. Then create a single reference for each using ASR. I would need a parent reference to create these on the RT. Then I would need one for the host which I would create/destroy as necessary. This adds up to 6 simultaneous references, which should be acceptable.

Can anyone think of a better way to do programatic referencing of DMA FIFOs? Perferably one that doesn't result in the creation of so many references. Please bear in mind that I really want to maintain the dynamic design of the application, to maximise the resue of the FIFO listening actors.

[Michael_Strain]

Hi Max,

Could you describe your system setup a little more?  Is the VI that is calling Open FPGA Reference on the RT Target, or on Windows?

The max number of RIO sessions that can be open at one time is normally 65535.  The exception to this is when you open a session over the network (ie using a resource string like: rio://hostname/PXI1SlotX rather than just PXI1SlotX).  Network sessions to PharLap and VxWorks targets are limited to 16 concurrent sessions.  Advanced Session Resources count as sessions with regards to those limits.

[MaxJoseph]

Hi Michael,

Many thanks for the reply! I am using a PXIe-1085 chassis with a PXIe-8133 controller running the latest RT version (18.1?). I have a 7965R FPGA with a 5761 front end module attached. My Host PC is running Windows 7 with LV2018 installed.

I am calling Open FPGA Reference on my RT when I initialise the actor there that manages the FPGA. I also call Open FPGA Reference on my Host (windows) when I initialise the actor there that sends commands to the FPGA. I make all my ASR calls on the RT from the 'parental' reference I created when I initialised that actor.

I currently open all my references with full rio://hostname/stuff addresses that I build from strings. I thought that adding hostname would give me more flexibility later on. I was worried that not adding hostname would lead to name clashes when I added more chassis' to my setup. Admittedly on a single chassis I don't need to include hostname at all!

Is it more usual to use PXI1SlotX as the rio address rather than the more formal rio://hostname/stuff? Does using the full rio:// address as the 'parental' reference on the RT mean that I am using the 16 limit rather than the 65535 limit?

I am very interested to hear about a 65535 limit to concurrent sessions, that would be loads for me! When I put a breakpoint in the function that calls ASR to connect to the RT FIFOs, I can manually choose when the next ASR call is made, while the rest of the system functions normally. On the first run since a restart, I get the error after I pass 4 ASR calls. On relaunch of the application the error occurs after fewer ASR calls each relaunch until I get it on the first call. A restart of the chassis allows me to call ASR multiple times again. From all this I got that I was probably not closing references and hitting the 16 limit faster as a result.

I will do some investigating and get back to you later today.

Many thanks again for the advice!!

[MaxJoseph · Accepted solution]

Good news everybody!

I just tried to change the original Open FPGA Reference call to use the local PXI1SlotX address, rather than the full rio:// address. I appear to be able to open as many references as I need on the RT and on the host.

I think it was as Michael implied when he said that network sessions are limited. I will keep testing but this appears to be the solution!

Thanks for all the help.

Max

[Intaris]

BTW, just an addendum to the infiormation regarding opening a network session.

If you are opening a reference to a device which is physically located in the same chassis as where your code is residing, DMA transfers and Control Read/Write functions will execute much more slowly if you use the URL-type of reference when opening the reference to the bitfile.

It's not only a number of sessions issue, performance will also be different if you involve the network stack.

[MaxJoseph]

Ah, thanks for the extra information, Intaris. I will be sure to open my references locally where possible.