Trouble shooting of FlexRIO & NI1483 w/ PCO camera-link CMOS

[volume2]

Hi, 

We have install the NI PXIe-7972R + NI 1483 adapter, and connect to PCO.edge 4.2 camera with camera-link interface. I just follow the user manual (http://www.ni.com/pdf/manuals/375502b.pdf), and use "1-Tap 10-Bit Camera with Frame Trigger.lvproj" switch to our target 7972R FPGA. I can successfully compile the FPGA target as Fig. "troubleshooting_1tap10_1.png". However, when I use the host vi that was not work as Fig. "troubleshooting_1tap10_2.png", it also tell me to recompile. I have already compile many times, it still doesn't work and continuous give the error of FPGA open. I also try the method mentioned in (https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019MITSA2&l=zh-TW) as Fig. "troubleshooting_1tap10_3.png", the result is the same, it's still doesn't work. Is there any solution for this condition, thanks?

Best,

Yong

[AlysaOng]

Hi，

Here are some links for your reference
https://forums.ni.com/t5/LabVIEW/FPGA-Error-63195/td-p/2810590

https://forums.ni.com/t5/LabVIEW/FPGA-read-write-error-63195/m-p/3204488

Try to debug the host to verify where the source of the error is. (using break points and single stepping, or by probing error wires). If limiting the code to where the error is originating from it will be easier to find the reason behind the error.

From this you could get the whole error chain (VI hierarchy from host to error source).
http://www.ni.com/documentation/en/labview-comms/2.0/fpga-targets/testing-fpga-applications/

[volume2]

Hi, 

Now I'm working on the FlexRIO PXIe-7972R + NI 1483 for the camera-link camera. I already installed and connect all devices properly. The camera I used is pco.edge 4.2, with full camera-link communication, support for 10-tap 8-bit data. I just modify the example code from "10-Tap 8-Bit Camera". Now, I can detect the camera clock as figure, and the module is enabled. I use the IO Module\CL Control 1 to send the trigger command. However, when I start to acquire the image and send the trigger, there is no any image transmitted. I also discover the IO Module\CL Frame, CL Line, and CL Data are not valid as figure. Is anyone know where might have problem? Thanks.

 

Best,

Yong

[volume2 · Accepted solution]

Thanks for your reply.I will try the method from the above link.  So far, I can run the FPGA in host. However, I have to open the FPGA VI first, and then open the host VI. There is still something weird.