05-31-2011 02:51 PM
how can i build a manchester coding in labview signal processing?
mean to say that how can i digitize my audio input.i waqnt to convert my audio input into manchester coded data format!!!
kindly post related VIs
regards
Solved! Go to Solution.
06-01-2011 09:51 AM
idma-
The 2 processes that we have using the Manchester coding format are here:
One is for a FlexRIO http://zone.ni.com/devzone/cda/epd/p/id/6400
The other is for LabVIEW FPGA http://zone.ni.com/devzone/cda/epd/p/id/6126
I would check out these tutorials and take some of ideas if you are trying to apply it to a more general audio application.
In manchester encoding a bit is represented by a rising or faling edge rather than a high or low.
a low or false value is represented by a falling edge (true to false)
a high or true value is represented by a rising edge (false to true).
Hence:
1 0 1 0 1 1 0 0=
01 10 01 10 01 01 10
If your input comes in as a binary array, you need to replace every ellement with the corresponding two elements.
Note that for a particular output baudrate, your clock must be twice that frequency.
Here is a samlpe pic that may help too: http://forums.ni.com/ni/attachments/ni/170/501520/1/doc-2824%20Update%20output%20state.JPG
This is one way other customers have tried to accomplish the task
I hope this helps 🙂
06-01-2011 01:59 PM
can i implement this line coding using advanced signal processing toolkit??
as i am doing my work using this thats y i will be more comfortable by using these toolkit.....please guide me in this regard
best regards
06-01-2011 02:06 PM
I believe you should be able to do this using the ASPT 🙂
Give it a try like the examples above and the pictures and see if you are able to get it going
06-01-2011 02:08 PM
are the controls and functions used in image available in ASPT??
will this logic works as it is for fpga??
06-01-2011 02:10 PM
I believe so, or atleast the logic behind them are. 🙂
This logic will work for FPGA as well!! 🙂
06-01-2011 02:12 PM
can u provide me example vi??
06-01-2011 02:18 PM
idma-
Check out the LabVIEW FPGA example http://zone.ni.com/devzone/cda/epd/p/id/6126
Basic example showing generation of a Manchester encoded data stream. The data to be sent is generated in one loop and passed to a FPGA FIFO. The subVI which generates the Manchester data stream reads the data bytes form the FIFO and passes them to the digital output. The subVI prepends a simple header to each data packet which allows a reader (see next example) to synchronize and acquire/parse the data. The header consists of a thee half bit pulse followed by a one half bit pulse. The three half bit pulse is not a valid component of regular Manchester encoding and can therefore be differentiated from the rest of the protocol. In addition it can be used by the receiver to to easily measure the bit rate of the protocol. By dividing the length of the three half bit pulse in half (3/4 of a bit), the receiver has a measure to differentiate between full and half bit pulses in the rest of the protocol.
An extension of the previous example which adds a Manchester receiver subVI. You must physically wire the digital output channel to your input channel to loop back the data outside the I/O connector of your FPGA R series card or C series module. The Manchester receiver subVI is expecting the data packet to be prepended by a header as explained in the previous section.
I will see if the is a more precise example but this should help
06-01-2011 02:38 PM
06-01-2011 03:14 PM
work done by me uptil quantization.....after this i have to implement line coding!!!
help reqiured
regards