join split for 5 I16/I32 numbers

[SaraBaber]

Hello

I actually want to join 5 numbers of type I16 or I32 and later on split those on fpga side! I tried it and I was able to combine 5 I8 numbers, but when it comes to I16 I cannot do this. As postive as well as negtive numbers should be same after spliting as before joining!

I have attached a VI in which I did it for I8!IN this I tried changing the type but then the output isnt correct for both positive and neg numbers. Can you please help me with I16 type of join/split for 5 numbers!

sara

[crossrulz]

Your problem with trying to join 5 16-bit numbers is that there is no data format that can support it.  The largest integer data type is a 64-bit, which can only store 4 16-bit numbers.  And for the 32-bit numbers, the 64-bit can only hold 2.

[SaraBaber]

So in other words its not possible to join 5 numbers or more of I16 or higher data type? Am I right?

Thanks

Sara

[crossrulz]

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@SaraBaber wrote:

So in other words its not possible to join 5 numbers or more of I16 or higher data type? Am I right?

Thanks

Sara

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Correct.  You can get 4 I16s into a U64, but you can't go any further than that.

Just playing around, it looks like you will loose your MSBs if you try to go too far with the joining.

[SaraBaber]

thats right! loosing the data on the upper bit while joining!IF in case it works by any of your experimentation, do let me know

 thanks alot!

Sara

[RavensFan]

Why are you trying to join 5 numbers together to just split them apart on the other side?  There might be other ways of accomplishing whatever it is you are trying to do with joining/splitting.

[OlivierL]

You mentionned FPGA in your original post, why not simply pass the 5 distinct numbers through a FIFO or 5 different controls on the FPGA front panel? 

[SaraBaber]

Hello

Yes I am trying to send data from HOST to FPGA! and that data is continous as its using spline interpolation!

I have to fit in the code for five motors! As I am using Crio 9074 so I am having only three DMA channels and have limited spae on FPGA!

For this purpose I worked with another NI engineer to fit in my code for 4 motors. It occupied space of alost 95%, but when I added 5th motor, even after condensing the code to maximum its not fitting in, So I thought maybe if I will remove 2nd DMA channel that I used for 5th motors it will fit it, but I cant cz for first 4 motors I used join split function and therefore used 1 DMA channel for four motors!

So the main purpose is now fitting in the code whether with or without using join split function!

I reposted my question again on that forum but because it was closed as the problem so solved so it wouldnot be entertained! If you can please help me getting back to thatparticular engineer or you can solve my issue!

Here is the link to my previous forum:

http://forums.ni.com/t5/LabVIEW/compilation-error/td-p/2366936

It was really helpful!I made some changes in it and it was perfectly fine for four motors that is my fpga3 VI in project

Now when I added fifth motors, that is fpga4 reduced.vi, on which I am currently working, its getting out of limit again! and I cannot find a way to further squeeze in my code!although I have made the drive staus loop common to unlike in fpga3(that I prefer). It would be better if I am having seperate enable buttons for each drive like in fpga3 for four motors code!BUt even If I avoid that Its not fitting in!

I am also posting my fpga code. Please have a look! I cannot avoid the corecion dots at some places the reason is explained in block diagram!

Thanks alot for support

Sara

[RavensFan]

This sounds a lot like a conversation I had with a LabVIEW programmer doing some FPGA work for a project for us.  He was doing 1 DMA per channel of data, and was going to bump into the limitation of having only 3 channels because there are only 3 DMA's, but we were looking to had a 4th channel of data.

I had suggested a couple of solutions to this.  1.  Combine 2 pieces of data into a single element.  Then you can pack 4 channels of data into 2 DMA channels.  That is basically what you are already doing, so it probably doesn't help you.  (Since your issue is with space, you'll need to figure out if going from 2 DMA channels to 1 DMA channel saves you space.  Or if it is 5 instances of code vs. 4 instances is what is eating up space.

2.  The other solution is to pack the data into the same DMA channel passing each channel individually in order in time, then doing something special to distinguish the elements from each other.  If you have the extra bits, you could use a high bit set to distinguish which is the data from the first channel in a group of data being passed sequentially in time.  Later elements have the high bit set to low.  If you have several extra bits available in the datatype you don't need for the data, you could use them in a binary fashion to set an address/flage for each element individually.  With 2 bits, you could distinguish 4 different pieces of data from each other.  With 3 extra bit, you could distinguish 8 different pieces of data with each other.  Of course this method requires that the DMA communication is able to run at a fast enough speed to keep up with the data being passed.

[GregFreeman]

I'm not sure if this is acceptable for the kind of control/application you are doing. And, I don't know your data rates so I'm not sure if this could keep up on the RT with the speed the FPGA needs to process at. It seems you keep trying to cram elements into a FIFO by making it bigger. But why don't you configure your FIFO for less elements and write in chunks to the FIFO from a loop on the RT? For example, let's pretend you have a 100 element array. Configure your FIFO for 10 elements and write 10 elements at a time to the FIFO. 

I will say, I often recommend my customers spend more money on a better controller. I've been burned by the embedded cRIO controllers more than once. I end up spending more money trying to optimize software to handle the data size and throughput than I would have just purchasing better hardware.

Edit: woops, I meant pick a chunk size that divides evenly into your array size