Can the M-series internal multiplexer sequencer be used to sequence external multiplexers?

[ImAlsoGreg]

Hello NI community.

I have been using a set of AI-32 M-series cards to digitize independent streams of data at 32 kS/sec.  The signal source is a set of 256 very low-current voltage signals (action potentials in the brain of a rat running in a maze).  These signals are buffered by unity gain amplifiers on a tiny PCB attached to the rat's head.  The buffered signals are then sent through 256 extremely fragile 3-meter long cables to another set of filters and amps; the output of that amp stage is then sent to my NIDaq cards, and I use the c API for my acquisition and analysis.

I would like to cut down on the number of cables in that 3-meter bundle, so I am looking into the possibility of multiplexing.  The multiplexing itself seems simple enough, but it looks like demultiplexing is very tricky, requiring a bunch of sample-and-hold amplifiers all synchronized with the multiplexer gate sequence.  I described the whole idea in more detail, with a figure, here: http://electronics.stackexchange.com/questions/22521/does-analog-time-division-demultiplexing-need-a...

Someone suggested to me that I forgo my own demultiplexing.  Simply fork the multiplexed signal to all 32 AI channels of the NIDaq card.  Since the NIDaq card multiplexes its inputs through its ADC, it will sample each line only within the time window when the signal on that line actually carries the appropriate data.

But I think in order for this to work, I would need access to the internal sequencing (the digital gate signals that address the multiplexer) of the DAQ's multiplexers.  If I simply take the master timebase, count the cycles and decode the count into a gate sequence, then it seems like I may have a phase offset issue.  That is:

How do I know whether the DAQ card is counting this way:

Time:  0  1   2   3  4   5  ...  27   28   29   30   31   32   33   34   35

Seq:    0 ,1, 2,   3, 4,  5....   27,  28,  29,  30,  31,   0    1     2     3

Or this way:

Time:  0   1  2  3  4  5  ...  27  28  29  30  31  32  33  34  35

Seq:    2  3  4   5  6  7       29  30  31  0    1   2     3   4    5

So, is there a way for the user to have access to that sequencing data?

Or is there a way that I could safely count some clock signal in the card, and decode it in the same way that the card's multiplexer's sequencer decodes it?

Thanks very much for any advice you can offer!

-Greg

[Dan_N · Accepted solution]

Hi ImAlsoGreg,

First, I have to say, that's a really cool application you're working on. 

I have a couple of questions for you: What M-series card(s)are you using, and do you need to sample the data at 32 kS/sec? The easiest way for you to accomplish what you are describing here would be to wire the output of your mux to one AI channel on your DAQ, and then sample that channel at (number of channels)*(your sample rate). In this way, you're still reading in each multiplexed signal, but on one channel instead of 32 (or however many channels the max sample rate on each card allows you to sample).

You'll need to synchronize the DAQ analog input with the data coming from your mux, which could be done by sharing a timebase (such as an exported counter from your M series card) and start trigger between the two devices. That way, you'll know what order the channels are being sampled in, and can then use the C API to break the incoming data into a separate array for each channel. 

You could also pull the data in on all 32 channels of your M-Series card and then use the card's mux to split it. However, you would then need to synchronize the convert clock (information about which can be found here) with your mux, to make sure that you are receiving the correct data. There have been some issues with synchronizing external convert clocks in M-Series cards, so again, I would recommend that you use one channel and split the data in C. 

Best,

Dan N

Applications Engineer

National Instruments 

[Dan_N]

Hello again,

As a quick follow up, if you wanted to do the external convert clock synchronization across all of the channels, you would need to do something very similar to this example. If your mux, convert clock, and sample clock all shared the same timebase as in this example, that would accomplish what you were hoping to do with the 32 channel demuxing.

Best,

Dan N

Applications Engineer

National Instruments 

[ImAlsoGreg]

Hey Dan,

Hah - thanks.  Yeah, I really like the application too.  I'm using the NI PCIe-6259. 

Thanks so much for your advice.  This idea of recording at a faster rate on a single input channel is really clever, and I was just about to try to implement it.

But I realized that... I actually need analog access to independent channels /before/ the signal gets to the NIDaq cards, for example so that I can listen to a single channel on an audio monitor and/or display a single (reconstructed) channel on an oscilloscope.

So I think I am going to try to do my own sequencing, route the signal to a parallel set of sample-and-hold amplifiers, and hopefully filter out the transients.  If I have the signals demultiplexed and reconstructed, I will probably just feed them straight into the 32 channels as I had been doing before (in the pre-multiplexing days).

I'm disappointed that I'm not forced to try your idea.  But we'll see how it goes 🙂  I may yet end up having to sync up to the card's multiplexing clock.

-g

[Dan_N]

Hey Greg,

Sounds good, if that's what your application requires. If you have any other questions, post them here and I'll be happy to answer them, and if you do end up giving any of my suggestions a shot, let me know how it goes for you. Good luck!

Best,

Dan N

Applications Engineer

National Instruments 

[ImAlsoGreg]

Hey Dan. Quick followup question. I would still like to do my own multiplexing in analog, but I'm considering using the card's clock as my timebase, if it's the case that the clock gives some info about when the card expects a valid input. Is that the case -ie does the ADC in the card only sample during the high phase of the clock or only during the low phase, or do things not work this way? I think my demultiplexer will have glitches near channel-switching time and I'm hoping I can hide those from the nidaq card through timing. Thanks!

[Dan_N]

Hey Greg,

The card will take samples during the high pulse of the sample clock signal, but the ADC actually digitizes the voltage at each separate channel in order during the high pulses of the convert clock signal, as explained in this document. If you need any clarification, feel free to ask.

Best,

Dan N

Applications Engineer

National Instruments 

[ImAlsoGreg]

Thanks Dan.  Yep - that part I think I understand.  The sample clock is going at 32 kHz (period is 31 microsec), and maybe.... ~95% duty cycle, if sampling is only allowed to happen during sampling clock high phase - or from the figure it looks like maybe low-to-high transition signals the beginning of a scan of all the lines.

I think the thing more important to me is the convert clock's duty cycle.  The clock that I would use to pace my demultiplexer is the convert clock - which is going at 1.024 MHz (32 kHz per channel * 32 channels) (period is 976 nanosecs), and I'm wondering in particular about the meaning of the duty cycle (in the figure it looks like about 50%) of that convert clock.  Is convert's high phase the phase when the ADC is measuring a single given channel, and ADC is measuring nothing (just waiting for the multiplexer on the nidaq card to connect to it the next channel) during low phases?  Or does ADC work on a given channel during only low phases, and pause during high?

Or is the ADC sampling whatever channel it's currently hooked to for the entire 975 ns of convert clock period?

[Dan_N]

Hi Greg,

Your first thought is correct; the conversion at the ADC occurs when the convert clock is high. 

Best,

Dan N

Applications Engineer

National Instruments