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We appreciate your patience as we improve our online experience.
09-27-2006 07:24 AM
09-28-2006 01:35 AM
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09-28-2006 02:10 AM
Hi Babay,
I copied the following from the NI High-Speed Digitizer Help:
In the decimation method, the ADC samples at the rate of the onboard clock and then sends its digital data to a decimator that essentially discards samples at a specific interval to achieve slower effective sampling rates. The valid sampling rates are always an integer divisor of the onboard clock. For example, if the onboard clock is 100 MHz but you want to sample at 25 MS/s, you must use decimation. The decimation method would discard all data except for every fourth datapoint to achieve exactly 1/4 of the maximum sample rate (or onboard clock rate).
Some oscilloscopes use the divide down clock method. In this method the onboard clock is sent through a series of clock dividers, and then that clock is sent to the ADC. Typically, the decimation method is preferred over the divide down clock method.
Note NI high-speed digitizers support the decimation method but do not support the divide down clock method. |
You can find this section in NI High Speed Digitizers Help->Fundamentals->Clocking->Sample Clock
The decimator has 16 bit, that means the sample rate range starts at 250MS/s and ends at 3,815kS/s.
I hope it helps.
Evrem
NI Switzerland
09-28-2006 03:07 AM
10-09-2006 02:07 AM
@EYCH wrote:
Hi Babay,
I copied the following from the NI High-Speed Digitizer Help:
Decimation Method
In the decimation method, the ADC samples at the rate of the onboard clock and then sends its digital data to a decimator that essentially discards samples at a specific interval to achieve slower effective sampling rates. The valid sampling rates are always an integer divisor of the onboard clock. For example, if the onboard clock is 100 MHz but you want to sample at 25 MS/s, you must use decimation. The decimation method would discard all data except for every fourth datapoint to achieve exactly 1/4 of the maximum sample rate (or onboard clock rate).
Divide Down Clock Method
Some oscilloscopes use the divide down clock method. In this method the onboard clock is sent through a series of clock dividers, and then that clock is sent to the ADC. Typically, the decimation method is preferred over the divide down clock method.
Note NI high-speed digitizers support the decimation method but do not support the divide down clock method. You can find this section in NI High Speed Digitizers Help->Fundamentals->Clocking->Sample Clock
The decimator has 16 bit, that means the sample rate range starts at 250MS/s and ends at 3,815kS/s.
I hope it helps.
Evrem
NI Switzerland
Ok. If the decimator has 16 bit, then the sample rate range should start at 250MS/s and end at 3,815kS/s. But that's wrong. I set different s.r. and got following results (actual s.r.): scope->setSampleRate(100) //actual sample rate is 954 scope->setSampleRate(1000)//actual sample rate is 1000 scope->setSampleRate(1500)//actual sample rate is 1500.01 scope->setSampleRate(1501)//actual sample rate is 1501.01 scope->setSampleRate(100059)//actual sample rate is 100080 These values cann't be calculated by dividing of 250 MHz on any integral value. Furthermore I didn't find any appropriate attribute for Decimation except R/O Combined Decimation, but appearently this is not what I need.Does anybody have an idea?