Welcome to the IP Integration Node

[Newton_Petersen]

The LabVIEW FPGA IP Integration Node provides a wizard interface and cycle accurate simulation within the LabVIEW execution environment for third party IP. This thread is intended to foster discussion about the project. Please post your questions, suggestions and applications here. Our team including R&D, marketing, and support will actively monitor this discussion.

Thanks,

Newton Petersen, Senior Engineer, LabVIEW FPGA R&D

[AndyBrown]

Are there any limitations to what this block can emulate?  I did a quick attempt to integrate a simple MACC (multiply-accumulate) configuration for a DSP Block. I get only zeros out of the data_out port.  Do I need to do something special to emulate a DSP Block other than attach my VHDL file?

[vwan]

Hi Andy, you're right. You really need to do something special to DSP48. But fortunately, it's very simple. You only need to add the following to your VHDL:

library unisim;
use unisim.vcomponents.all;

This is also needed when you use ISE to simulate the DSP48. But it's not necessary for synthesis.

BTW, you might need to change the signal name reset to another one, such as rst. Because LabVIEW FPGA reserves this name for special usage. Please read the help(click Help button on configuration dialog) document for details.

[AndyBrown]

Thanks, that solved the issue.

[AndyBrown]

We've been playing around with the IP Integration node a little and found one annoying characteristic.  If you have a syntax error in the HDL code the 'Generate Simulation Model' step hangs.  The only way to get back is to click the Cancel button and then go back into the IP Node's properties. This cancels all the settings done for IP Name, adding source files, making the right one top-level, and setting the relative/absoulute path settings.  Typically we have our HDL editor open and when we have a syntax error we go back on fix it and save it.  It would be much simpler to be able to click the generate button again without having to close down the dialog.

Andy

[Newton_Petersen]

Excellent feedback. Keep it coming... We'll get this resolved during productization. In the meantime, you can try to syntax check the source before importing into lv fpga. In ISE there is a specific option for "Check Syntax" which should be relatively quick.

[--thatguy]

I tried replacing an HDL node with an IP Integration Node but I'm getting a number of errors while in the mapping phase of my compile.

I've included a simple project where the FPGA vi has the working HDL node disabled and the IP Integration node enabled so that you can play with both.

What am I doing wrong?

Thanks

[vwan]

You you fix this issue by renaming the vhdl file to be the same as the entity name in it, or you can also rename your entity name to be consistent with the file name. We recommend always keeping the entity name the same as the file name where the entity is in. Anyway, it's a bug of the IP Integration Node and we'll fix it during productization. Thanks for reporting this to us.

[--thatguy]

Thanks that solved it!

[--thatguy]

We really like what we're seeing with the IP Integration Nodes.  Two suggestions though:

1) I can't always remember what my exact data types are when I config the IP Integration Node (especially those pesky fixed-point numbers).  Would there be a way to add a shortcut menu item that loads the last page only?

2) I'm not sure why but the HDL node appears to support the partial mapping of a dsp output to a port but the IP Integration Node does not.

The following works in the HDL node:

P(47 downto 17) => open,                    --  The IP Integration Node throws an error here.  I have to map it to a dummy signal.

P(16 downto 0) => data_out,

It's not a big issue, but now I've got to go through and tweak a bunch of files I'd rather not touch.