Welcome to the IP Integration Node

[Newton_Petersen]

Generics are not officially supported however we are trying to get this implemented in the actual release.

The VHDL portlist must only contain std_logic and std_logic_vector ports. You then select on the last page of the IP Integration Node how LabVIEW should interpret those bits. I would recommend taking your VHDL and creating a wrapper entity that converts the integer arrays to std_logic_vector. Then in LabVIEW have this mapped to a Boolean array. Then post process this boolean array into sub-arrays the size of the original vhdl integer elements. Then convert these Boolean sub-arrays into integers using the "Boolean Array To Number" function. These conversions are merely datatype reinterpretations and do not consume any resources (besides development time:-).

[sed_y]

well, i do have some issue with wrapper file. however,presenly these is one more issue.

i was trying to implement convolution in ip node. although,earlier i wrote a vhdl program using integer arrays, it wont work without creating wrapper file.

so, i wrote another code using std_logic_vector in ascending range( lsb left,msb right) as input,output. but, i have seen that in convolving say [ 3 2] with [ 4 5 6], instead of [ 12 23 28 12] as result,

i was getting all blank. however, if i enter the inputs in descending range in labview ( vhdl code unchanged), i get correct result( read in descending range way again).

any explanation?

this made be experiment with how labview takes array range . again, i have very conflicting results.

i have attached relevant project, with 2 vi's convolution_by_by_bit and array_dir ,with vhdl files.

please run them,and see the results. i have also put snapshots of what is expected,and Modelsim simulation results.

thanks

sidharth

signal and image processing lab

UTD

[Newton_Petersen]

Good point. I believe your experiments have reverse engineered how the std_logic_vector is defined in LabVIEW FPGA: std_logic_vector(kLength-1 downto 0). So when you have a port on your vhdl like std_logic_vector(0 to nx-1), I believe this effectively reverses your bits from an indexing perspective. Bit kLength-1 of the LabVIEW signal is now bit 0 inside your entity. I believe the moral of the story is the std_logic_vectors on your wrapper file should be using the downto indexing in order to stay consistent with how lv fpga orders the bits.

[patlolla]

Hi NewtonPetersen,

I am using IP node for my LabVIEW FPGA project. I am getting declaration errors when I try to use fixed point numbers in VHDL code.

I will explain this problem using simple VHDL program of adding two unsigned fixed point numbers and assigning the result to a fixed point number.

Errors for the program shown below

ERROR:HDLCompiler:69 - "fix_pt.vhd" Line 9. u_ufixed is not declared
ERROR:HDLCompiler:69 - "fix_pt.vhd" Line 10. u_ufixed is not declared
ERROR:HDLCompiler:69 - "fix_pt.vhd" Line 11. u_ufixed is not declared

my vhdl program is:

library ieee_proposed;      --library which contains fixed_pkg
library ieee;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;

entity fix_add is
  port(

        a: in u_ufixed(3 downto -3);   --Taking wordlength as 7 and integer length as 4
        b: in u_ufixed(3 downto -3);     --Taking wordlength as 7 and integer length as 4
        c: out u_ufixed(4 downto -3)   --Taking wordlength as 8 and integer length as 5

        );
end entity;

architecture behaviour of fix_add is
begin
  c<=a+b;
end architecture;

The same program compiled and simulated successfully in Model SIM, ofcourse I changed the library declarations,as ModelSIM contains 'fixed_pkg' in different library.

I thought these errors are occuring due to non declaration of libraries,but I declared libraries in my program .

Is there any mistake in my declaration ?What is problem with this program?

Thanks.

[Newton_Petersen]

When I look in C:\NIFPGA2009\Xilinx\ISE\vhdl\src\ieee_proposed\fixed_pkg_c.vhd, I do not see a u_ufixed type. There is a ufixed type; perhaps it is the same thing. Just a reminder, in the IP Integration Node, all the toplevel ports must be of type and format: std_logic_vector(kLength-1 downto 0). You can use whatever types you want below the toplevel. I also recommend compiling your VHDL code in a xilinx ISE project before trying to integrate it into the IP Integration Node as it will be easier to track down syntax errors.

[patlolla]

Thanks it worked ,I changed the u_ufixed to ufixed.

[thill]

I have two issues to bring up about the IP integration node.

1.  If a compile is unsuccessful, the user has to rebuild the IP integration node completely.  This isn't a very big deal if the number of files being referenced is small, but if it's large then it becomes fairly time consuming to regather the files.  There should be a way to save the list of files being referenced so that the user doesn't have to find all of the files every time until the compilation is successful.

2.  I am getting the following error after a fairly large compilation.

Generated simulation model successfully!
Error:<APPEND>
C:\Program Files\National Instruments\LabVIEW 2009\vi.lib\rvi\NIPI\dialog\BasicSetting\nipi_GetModuePortInfo.vi
<b>Additional Information:</b> The IP has no ports or the IP has expressions that this node doesn't support.

Any advice on this?

Thanks!

[Newton_Petersen]

For 1, good suggestion.

For 2, can you attach the VHDL that displays this problem?

[thill]

Newton,

I can't post all of my code due to IP restrictions.  Here is the top-level entity declaration. I'm not too sure if this will help you out.  I was able to successfuly use the IP integration nodes with the sub-components of this design, so my guess is that the error is somewhere in doppler_one_path.vhd

entity  doppler_one_path is
port(
  clk               : in  std_logic;
  srst              : in std_logic;

  ready_in           : in std_logic;
  data_valid_in     : in std_logic;
  data_in           :  in std_logic_vector(35 downto 0);

  ready_out          : out std_logic;
  data_valid_out    : out std_logic;
  data_out           : out std_logic_vector(35 downto 0);
 
  delta_t           : in  std_logic_vector(49 downto 0);
  doppler_scale     : in std_logic_vector(24  downto 0);
  awgn_scale        : in std_logic_vector(24 downto  0);
  doppler_tap_in    : in std_logic_vector(24 downto  0);
  doppler_tap_index : in std_logic_vector(9 downto  0);
 
  doppler_tap_set   : in std_logic;
  skip_doppler      : in  std_logic
);
end doppler_one_path;

[vwan]

thill,

The IP Integration Node reported this error because the xilinx tool couldn't extract the ports information from your  top level vhdl file. I created an empty module with your port list:

library ieee;
use ieee.std_logic_1164.all;

entity  doppler_one_path is
port(
  clk               : in  std_logic;
  srst              : in std_logic;
  ready_in           : in std_logic;
  data_valid_in     : in std_logic;
  data_in           :  in std_logic_vector(35 downto 0);
  ready_out          : out std_logic;
  data_valid_out    : out std_logic;
  data_out           : out std_logic_vector(35 downto 0);
 
  delta_t           : in  std_logic_vector(49 downto 0);
  doppler_scale     : in std_logic_vector(24  downto 0);
  awgn_scale        : in std_logic_vector(24 downto  0);
  doppler_tap_in    : in std_logic_vector(24 downto  0);
  doppler_tap_index : in std_logic_vector(9 downto  0);
 
  doppler_tap_set   : in std_logic;
  skip_doppler      : in  std_logic
);
end doppler_one_path;

architecture rtl of doppler_one_path is
begin
end rtl;

The IP Integration Node worked for this mockup case. So I recommend you to review your top level vhdl file to see if there are any expressions that Xilinx doesn't support well.