Welcome to the IP Integration Node

[vwan]

Hey tsileo,

After you install the IP Integration Node, you should be able to find it at Addons palette if the VI is under FPGA target. The source files should be in <LabVIEW>\vi.lib\rvi\NIPI. Please let me know if you still cannot find it.

[TimS.]

Hi vwan,

It turns out that my palette set for PXIe-5641R wasn't set up correctly after it was installed. I discovered from the "edit palette set" option that there are different palette sets for each FPGA target. After you pointed me to the correct NIPI directory I just had to add the "NIPI.xnode" to the addons palette and now it works. Thanks for the help.

Tim S.

[JDubb007]

Hi,

   I recently used the IP Integration Node to import a VHDL module into LabView.  The code is a Synchronous Serial Interface, which generates a Strobe and a burst of enable pulses.  The number of enable pulses is dependent on the number of bits I am receiving.  I created the same interface completely within LabView FPGA because I wanted to compare the Synthesis results of my VHDL code versus those from the LabView FPGA module.  I am using an NI 7813 RIO card which has a Virtex II FPGA and I connect the outputs from the 7813R to an SCB-68 Shielded Connector Block.  The VI running with the IP Integration Node works, but I noticed that my strobe signal doesn't look that great when viewed on an oscilloscope.  The amplitude is slightly attenuated and does not look like a square wave.  It's also very difficult to get a stable trigger on the oscilloscope.  My second VI, which does not contain the IP Integration Node works perfectly!  I don't have any issues trying to trigger on any of the signals on the oscilloscope and the strobe is a much cleaner square wave.

The main difference between the two VIs are as follows:

VI w/ IP Integration Node                                                      

• Runs on a 28MHz enable generated from the default 40MHz
  
• Runs with the IP Integration Node in a Single Cycle Timed Loop
  

VI without IP Integration Node

• Runs on the default 40MHz clock
• Runs using a While Loop with a few nested Stack and Case Structures and Wait VIs
  

I thought that perhaps the the 28MHz may be contributing to the difference in outputs however, I changed the VI to run on the default 40MHz.

1.)  Has anyone experienced this type of problem while using the Integration IP Node?

2.)  Is it possible that the problem is actually, due to the Single Cycle Timed Loop?

      I was considering modifying the second VI to use a Single Cycle Timed Loop to check.

Thanks

[Newton_Petersen]

Hi,

I love hearing about when something works in G but not in VHDL , but we should be able to get it to work with either methodology. One issue I recently ran into was someone using the "Set Output Data" method on a digital output but not also using the "Set Output Enable". You could see the intended waveform on the scope, but it was weaker than it should have been. Note: if you just write to an I/O Node (not a method node) it should do both the data and enable methods implicitly behind the scenes.

Another thing to check is just how fast the signals are toggling. The DIO on most of our R-Series boards is protected and so you can only toggle in the couple MHz range and still get a relatively clean signal.

That's all I can think of at the moment. For debugging purposes, it always helps to make things as simple as possible and then build up from there.

Feel free to post the code. The issue may just jump out at someone if they see the code...

[A.N.Other]

Firstly, let me congratulate you all on a very good and usable tool. I'm finding it much easier to use than the HDL and CLIP nodes.

My queery is whether or not there is a limit on the number of IP nodes you can include in one VI? I'm needing to put in 3 but I can't target any VHDL files in the third one. Is this a limitation of the tool or am I doing something stupid (which is always a possibility 🙂

Cheers,

Andy

[vwan]

Hi Andy,

We don't have such limitations. We actually have used more than 3 IPs in one VI before. What did you mean when you said cannot targeting any VHDL files? 

[A.N.Other]

When I place the 3rd IP node in the VI and go into it to add files, the file browser window opens but when I click on the VHDL file I want to include, the window closes without the file having been added.

Andy

[vwan]

Hmmm, it is either a bug of ip integration node or an issue of your system. I recommend you restart the system and try again. Please let me know if you ran into the same issue.

[A.N.Other]

Ok, that's strange, it's now decided to work fine, even though I did exactly the same thing as yesterday.My computer clearly just doesn't like Mondays...

Thanks for the help,

Andy

[JDubb007]

I started working completely within Labview FPGA to get around this problem, but I anticipate needing the IP Integration Node further down the line.  One thing that contributed to the problem was generating two separate loops.  One generated an enable in a seperate while loop and I used that signal as input to the IP Node w/in a Single Cycle Time Loop.  When I changed the design to generate all the signals within the Single Cycle Timed Loop, my signals looked much cleaner when viewed on a scope.

The code below generates a Strobe and Clock enable output.  The STB_OUT signal appears attenuated when viewed on an oscillocope.  The Stb signal is toggling pretty slow, <1MHz.  I was actually writing to the I/O Node (not a method node), but tried switching to an I/O Node and saw the same problem.  The code is running using the IP Integration Node inside a Single Cycle timed loop clocked on 28MHz, derived from the default 40MHz and I am writing the data to an I/O Node.  Is there any performance limitations when writing only to an I/O Node as opposed to the Method Node?  What are the benefits of using a Method Node as opposed to an I/O Node?

LIBRARY IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

ENTITY ssi is
  GENERIC (CLK_PLS_CNT: integer := 15);
   PORT (
     RST           :  IN STD_LOGIC;
     CLK           :  IN STD_LOGIC;
     CMD           :  IN STD_LOGIC;
     STB_OUT       :  OUT STD_LOGIC;
     CLK_PULSE_OUT :  OUT STD_LOGIC
   );
END ENTITY;

ARCHITECTURE behavior of ssi is

  CONSTANT Init_Cnt        : STD_LOGIC_VECTOR(25 DOWNTO 0) := "00"&x"000AF0";
  CONSTANT Start_Stb       : INTEGER := 2800;
  CONSTANT Stop_Stb        : INTEGER := 2744;
  CONSTANT Start_Clk_Pulse : INTEGER := 2688;
  CONSTANT Stop_Clk_Pulse  : INTEGER := 2045;
  CONSTANT Finished        : INTEGER := 0;
 
  SIGNAL   istb          : STD_LOGIC;
  SIGNAL   iclk_pulse    : STD_LOGIC;
  SIGNAL   nco_1mhz      : STD_LOGIC_VECTOR(5 DOWNTO 0);
 
  SIGNAL gen_pulse_cnt : STD_LOGIC_VECTOR(25 DOWNTO 0);

  BEGIN

  STB_OUT       <= istb;
  CLK_PULSE_OUT <= iclk_pulse;
 
  STB_PRC: PROCESS (RST, CLK)
    BEGIN
      IF (RST = '1') THEN
          gen_pulse_cnt <= Init_Cnt;
          istb          <= '0';
          iclk_pulse    <= '0';
          nco_1mhz      <= (OTHERS => '0');
                   
        ELSIF rising_edge(CLK) THEN
            IF (gen_pulse_cnt = Finished) THEN
                gen_pulse_cnt <= Init_Cnt;
              ELSE
                gen_pulse_cnt <= gen_pulse_cnt - 1;
            END IF;

            IF (conv_integer(gen_pulse_cnt) = Start_Stb) THEN
                istb <= '1';
              ELSIF (conv_integer(gen_pulse_cnt) = Stop_Stb) THEN
                istb <= '0';
              ELSIF (conv_integer(gen_pulse_cnt) <= Start_Clk_Pulse and conv_integer(gen_pulse_cnt) >= Stop_Clk_Pulse) THEN
                      nco_1mhz   <= nco_1mhz + 1;                                        
                  IF (nco_1mhz = 27) THEN
                      nco_1mhz   <= (OTHERS => '0');
                    ELSIF (nco_1mhz <= 13) THEN
                      iclk_pulse <= '1';
                    ELSIF (nco_1mhz < 54) THEN
                      iclk_pulse <= '0';
                  END IF;
              ELSE
                istb       <= '0';
                iclk_pulse <= '0';
                nco_1mhz   <= (OTHERS => '0');             
            END IF;
      END IF;

  END PROCESS STB_PRC;
 
END behavior;