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Welcome to the IP Integration Node

Is there any performance limitations when writing only to an I/O Node as opposed to the Method Node?

No.

What are the benefits of using a Method Node as opposed to an I/O Node?

You have access to both the data and enable ports separately. Note: if a digital IO line is not 'enabled', it is tristated and so you will see a much weaker output than if the output is actively driven. If you used the IO Node, LV FPGA drives both the data and enable. The enable is driven with true. The data is driven with whatever is wired in.

Do you have a testbench for this VHDL? Its a little tricky to follow just by inspection. Also, do you have the VI you are instantiating this IP in (with project for IO).

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Ok I understand, the IO Method gives you more control over the outputs.  So if I had, let's say an I2C interface where a signal is bi-directional then the IO Method provides the ability to tri-state the output from the RIO card and re-enable it when necessary.

My testbench is somewhat involved and incorporates a lot of different modules so I cannot provide it, but here is a screenshot of the output waveform that is generated.  I have attached the Labview project

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Hello,

I'm trying to call VHDL code with differents methods and I got different problems/behavior for all of them:

                               HDL node                                        CLIP                                        IP integration node

                                                                                                                   full source code               top level HDL + ngc

Simulation               no simulation in LabVIEW    no simulation in LabVIEW            OK                                   incorrect

                              Obsolete in next release ?         

Compilation             -                                             OK                                        errors                                   errors

FPGA                     -                                             incorrect                                   -                                         -

The source code is of course always the same. Both execution on FPGA with CLIP and simulation with IP integration node with ngc return no data.

Compilation errors for IP integration node is a combination of undifined and redeclaration symbol in the wrapper file generated by NI...

Any ideas ?

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Hi all, I'm attempting to integrate some fairly horrific 3rd party VHDL (which usefully has all the comments in German) and I'm having a few difficulties pushing it into the IP Node. I think the problem may be being caused by the fact that the IP is defining its own customised libraries. Does anyone know if the IP Node can handle this or does it have to only use the IEEE libraries?

Thanks,

Andy

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The IP Integration Node should be able to handle this. You should add their libraries as the source files.

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Thanks for the quick reply. I'll keeping at it and see if I can make it play nice!

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It would be easier to investigate your issues if you can attach your source file. There is no reason that the simulation and compilation don't work.

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I'm afraid there are some licencing issues involved with posting them here. Could you send me your email address and I'll send you them that way.

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My email is vincent.wan@ni.com. Thanks

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Hello!

Our key customer has got some issue with using IP Integration node in LV 2009. He took some own VHDL code with files proba_struct.vhd and proba_struct.ngc. Logic of this code you can see in attach. pic1.

Then using IP Integration he has imported code to LabVIEW (project in attachment). Problem that his logic doesn't work.

I've tested his project on our eqipment. Result was similar. I'm not realy good with FPGA's IP. Please, could you help me understend what was wrong in the customers project.

You can see attach here: http://forums.ni.com/t5/NI-Applications-Engineers/LV-2009-IP-Integration-issue/m-p/1263088#M152808

Thanks

Regards, Ivan.

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