Welcome to the IP Integration Node

[Russia_]

Hi,

Problem was with customers VHDL compiler. He used 2 files one is VHDL cover and file project structure .ngc. IP integration doesn't read ngc files. When customer converted all project to VHDL. Logic in his LV project became work.

Regards

Ivan

[vwan]

Great. Just want you know that the IP Integration Node in LabVIEW 2010 can

support ngc file.

Best Regards!

-Vincent

[Russia_]

Hi Vincent

Thank you for information.

Our customer has got new issue. When he tried to integrate his IP to LabVIEW he has got error. The error became in compile process:

ERROR:HDLParsers:800 - "C:/NIFPGA~1/srvrTmp/LOCALH~1/UNTITL~1/NiFpgaAG_TimedLoopDiagram00000002.vhd" Line 304. Type of reset is incompatible with type of reset.

-->

Why it could happen? May be something wrong with his .vhd file?

Thanks

Ivan

[mangood]

hi

what is this warring and how to solve it
appear in lab view 2012

Warning: No port in the IP maps to the clock enable signal. If the IP is sequential, this situation produces inconsistent results between simulation and actual FPGA hardware execution. When emulating on a development computer, the IP executes only when the containing block diagram structure executes. When executing on an FPGA target, the IP always clocks in input values regardless of its place on the block diagram. If you place sequential IP in a Case structure, LabVIEW returns an error when you attempt to compile the FPGA VI.

To address this issue, ensure sequential IP has a clock enable port. Then, use this page to map this clock enable port to a clock enable signal.

this is the my code

--------------------------------------

Library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity DemoClipAdder is

    port (

          clk : in std_logic;

          aReset : in std_logic;

          cPortA : in std_logic_vector(15 downto 0);

          cPortB : in std_logic_vector(15 downto 0);

          cAddOut : out std_logic_vector(15 downto 0) := (others => '0')

        );

end DemoClipAdder;

architecture rtl of DemoClipAdder is

begin

    process(aReset, clk) begin

      if(aReset = '1') then

        cAddOut <= (others => '0');

      elsif rising_edge(clk) then

        cAddOut <= std_logic_vector(signed(cPortA) + signed(cPortB));

      end if;

    end process;

end rtl;

----------------------------------------------------------

best regards

[David_Staab]

mangood wrote:

hi

what is this warring and how to solve it
appear in lab view 2012

...

I haven't worked with LV2012, but I know that demo CLIP from older versions. Cycle-accurate simulation was added to LV in 2012, and that's probably what this warning is about. The demo CLIP was written long before that feature was available and probably doesn't map a signal to ports on the upgraded CLIP interface in LV2012. NI often fails to upgrade their examples to work with new features, and I'm sure this was overlooked when the CLIP interface schema was updated.

Unless you're planning to simulate this CLIP, the warning can probably be safely disregarded. If you do want to simulate it for some reason -- I recommend finding another example CLIP that was made to demonstrate the simulation feature instead -- you'll have to read up on the simulation interface in the LVFPG Help and add the appropriate ports to the CLIP yourself.

[mangood]

dear david:

i am new to lab view fpga so not all your word was  understand

but at least the code work well and no error happpen

i put the warring so ni may put some enhacement and member must note this in  case error happen

best regards

m.s

Message was edited by: mangood

[mangood]

hi

is ip integration node supprot multiplier between two std_logic_vector signal?/

i try it but i seem there is no supprot for this

so i just need to be sure!!!!!

regards

[sesquembriI2A2]

Hi,

I'm following the examples described here, but the Check Syntax of IP Integration Node hangs indefinitely. No warnings, errors or "Not Responding" signals appear until I try to cancel it. Then I get the following message:

"Checking syntax...

Error 1 occurred at Scan From String (arg 1) in niFpgaIPINodeElaborateResult.vi:7330001->niFpgaIPINodeConfPage3.vi

Possible reason(s):

LabVIEW:  An input parameter is invalid. For example if the input is a path, the path might contain a character not allowed by the OS such as ? or @."

IP Integration Node Properties window keep hung. I must kill all LabView process with task killer and open all again. I tried with the entity used in the CLIP example and happens again.

Any idea of what can be happening here? Any solutions?

Best Regards!

-Sergio

*EDIT: I'm using LabView 2013 f2

[davy.baker]

sesquembriI2A2 wrote:

Hi,

I'm following the examples described here, but the Check Syntax of IP Integration Node hangs indefinitely. No warnings, errors or "Not Responding" signals appear until I try to cancel it. Then I get the following message:

"Checking syntax...

Error 1 occurred at Scan From String (arg 1) in niFpgaIPINodeElaborateResult.vi:7330001->niFpgaIPINodeConfPage3.vi

Possible reason(s):

LabVIEW:  An input parameter is invalid. For example if the input is a path, the path might contain a character not allowed by the OS such as ? or @."

IP Integration Node Properties window keep hung. I must kill all LabView process with task killer and open all again. I tried with the entity used in the CLIP example and happens again.

Any idea of what can be happening here? Any solutions?

Best Regards!

-Sergio

*EDIT: I'm using LabView 2013 f2

I have a similiar problem as above with NI example "IP Integration Node.lvproj".  (i.e. hangs indefinitely with "Checking syntax..." after pressing the button "Check Syntax" with the IP Integration Node Properties (Page 3 of 6) on the "IP Integration Node.vi" example, using DemoClipAdder.vhd.    After waiting several minutes, and clicking cancel, I get the same message as above (Error 1 occurred at Scan From String... ...? or @)

Trying again (after killing/restarting labview) but skipping this step, and going straight to "Generate" gives the error:

Running: C:\NIFPGA\programs\Xilinx14_4\ISE\bin\nt\unwrapped\fuse.exe -nodebug -prj ipinodesim.prj conf4B34AD3BC304427D975CBDEE455132AC -o DemoClipAdder_4B34AD3BC304427D975CBDEE455132AC.dll -dll

ISim P.49d (signature 0x8ef4fb42)

Number of CPUs detected in this system: 8

Turning on mult-threading, number of parallel sub-compilation jobs: 16

Determining compilation order of HDL files

Parsing VHDL file "C:\NIFPGA\iptemp\ipin87440A5781CE43309DE5D83D3DC934CD\DemoClipAdder.vhd" into library work

Starting static elaboration

Completed static elaboration

Fuse Memory Usage: 99980 KB

Fuse CPU Usage: 234 ms

Compiling package standard

Compiling package std_logic_1164

Compiling package numeric_std

Compiling architecture rtl of entity DemoClipAdder [democlipadder_conf4b34ad3bc30442...]

Time Resolution for simulation is 1ps.

ERROR:Simulator:861 - Failed to link the design

Generated IP unsuccessfully. Fix the above error(s) or warning(s) and generate the IP again.

I am in LabVIEW 2013 SP1.

Best,
Davy