HP Loop Duration With MXI

[alekus]

Hello,

i would link a CRIO 9159 to a PXIe 1085 with a controller PXIe-8880.

For this i use a MXi card Ni-PXI-8364.

i have also a sync line between the RIO 9401 and the PXI-6229 ( in ai/PFI0).

So i have create a FPGA project with teh model "MXIe-RIO Chassis on Real-Time PXI" for the MXI communication and realise some simple test with veristand to see the "HP loop duration" variation. 

 with only veristand (without the FPGA VI) ans some PXI i/o i have a "HP Loop Duration" at :  5µs 

I add the FPGA projetc with only some output on the RIO side :     55µs on the "HP loop duration"

i modify my project for adding AI on the RIO : the "HP loop Duration" go to 170 µs.

i think that this values are very important, because i need to have a main loop at 1ms ( to run some Matlab models).

can it be possible to decrease this values of "HP loop Duration " ?

thanks

[Andy-C]

Hi alekus,

While I haven't run this exact benchmark your results look reasonable.

You are correct that the HP Loop Duration is a very important measure of system performance. The HP Loop Duration will increase as you continue adding inputs and outputs from the FPGA target. 

In my experience it should be possible to achieve a 1 kHz loop rate even with a significant amount of I/O on the FPGA. However, it may be worth testing yourself especially if you are accessing a large number of channels.

How many channels were you using during your tests?

How many more do you need in the final system configuration?

Best regards,

Andy

[alekus]

Hello Andy,

in fact i have all my I/O from the CRIO, but i have many part on the PXI .

I have 19 pakets on output and 13 pakets on input (on U64).

So my "HP loop duration" is at 720 µs.

FPGA MXI communication :       170µs

Model 1 Matlab :                         180 µs

Model 2 Matlab :                           80 µs

Model 3 Matlab :                           15µs

Model 4 Matlab :                           20 µs

Custom device for Checksum, CRC, counter for CAN and Flexray :      30 µs

Custom device with DLL from a supplier :                                            150 µs

CAN and Flexray sending and reading with NI-Xnet :                          ????

Custom device Engine simulation toolkit :                                              20 µs

Management of I/O on PXI ( Ai, AO, Di, DO ) :                                   ????

so in some case i have HP count that increase. Before, the FPGA Project use the XML Builder  and with it the HP Count increase very quickly and the actual loot rate decrease at 500 or 300Hz, so the custom device from my supplier stop working because it detect a loop at 2 ms and not 1ms .

so i have update the FPGA code to work wiyhout the xml builder and it's better because now i have no more error from the supplier's custom device.

But it's possible that i have to add some part and so i would try to decrease my loop duration ....

[Andy-C]

Do you need I/O from the MXI-RIO FPGA to be synchronous/inline with the rest of the system?

If not, you could try using the FPGA Add-on custom device which will read/write to the FPGA asynchronously:

https://github.com/NIVeriStandAdd-Ons/FPGA-Custom-Device

Have you tried moving the Data Processing Loop to another core? Have you tried moving your models to different cores? 

Are you running the PCL in Parallel or Low-Latency mode?

What is the DLL-using custom device doing? Is it Inline? Does it need to be?

Just a few questions which come to mind. Let us know how it goes!

Andy

[Robert__R]

Also note that the PXIe-8364 will have a little lower latency than the PXI-8364.  It's probably not enough to matter, but if you are buying more then I'd certainly switch.  Or if you have access to a PXIe version then it would be interesting to here whether you can tell a difference.

- Robert

[alekus]

Thanks for the information, i will try to test this custom device for FPGA.

after yes, i have try put the Data Processing Loop on the CPU 0, and the Model on CPU 1 and 2. But i don't see difference on the HP loop duration or HP count.

The PCL is in parallel, i have try the low latency mode but the result was a disaster .....

The DLL in a custom device is a C application with special model : the custom device read inputs, run the main loop of the C code, write the output .  it's an inline model Custom Device and yes for me it's need to be inline.

alekus   

[alekus]

hello robert,

thanks for this information.

i will try to see with NI if they can give us this card to test it and see if the differences are important.

alekus

[alekus · Accepted solution]

Hello,

so after many try, i have found the source of my problem.

In fact, is that i have 19 AI on  the Daq card PXi 6229, and 12 AI in the CRio FPGA code.

so i have an HP loop duration of 241 µs for the DAQ only and 170 µs for the CRio.

I have put all the AI on the Crio and now i don't have anymore my problem.

But on this i have do some measurement and i don't understand for the PXI 6229.

The specification card say that the convert time is at 7µs, but on my measurment i have 14µs :

Nb input :                 Hp loop duration ( µs)

3                                  16

4                                   30

5                                   44

8                                   86

10                                 114

19                                 241

24                                 311

32                                 423

have you an explaination ?

[luda.mattski]

Hi alekus,

Admittedly a really late answer, but maybe others who have encountered this issue will benefit from this response.  The specified 7 microsecond settling time for the 6229 is - as you noted - the settling time to within 1 LSB for the ADC.  This is the minimum convert time to ensure the specified accuracy.

VeriStand does not natively use this minimum convert time; rather, in HWTSP mode, it will let the NI-DAQmx driver decide which convert rate to use to ensure that your multichannel measurement completes within one tick of the PCL but doesn't alias between channels.  If you want to force VeriStand to use this minimum convert rate and take on a higher risk of aliasing, select "Maximum" for the conversion rate of the DAQ Device in your System Definition (help doc here:  http://zone.ni.com/reference/en-XX/help/372846L-01/veristand/cp_daq/).  With this change, you'll see more consistent behavior that should show a more linear relationship between the number of channels and the HP Loop Duration; that said, there will still be some nonlinearities due to the overhead of the VS Engine.