Building high reliability FPGA-based inverter control systems - Fail-Safe Control Reference Design for CompactRIO

[BMac]

This example provides a framework for control systems which must behave predictably in the event of a hardware or software failure.  The example demonstrates FPGA safe states and FPGA monitored watchdogs for the Real-Time controller.

By defining a safe state for all control outputs within the FPGA itself, you can create a control system with a high degree of immunity from hardware or software problems in the HMI, Real-Time controller, or Input modules. 

Note: The Code attached below is provided As Is.  It has not been tested or validated as a product, for use in a deployed application or system, or for use in hazardous environments.  You assume all risks for use of the Code and use of the Code is subject to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense

Fail-Safe Control Reference Design for CompactRIO

Additional recommendations:

• Follow this link to learn more about the LabVIEW Real-Time Watchdog hardware counters and how to use them: Using Watchdog Hardware to Recover from Embedded Software Failures (Real-Time Module)
• Include a hardware watchdog circuit on your mating board that connects to the NI general purpose inverter controller (GPIC). In the event that the sbRIO-960x FPGA does not service the watchdog within your time limit, disable the gate drive outputs to put the IGBTs/MOSFETs in a safe state. Also include an Enable signal that must be explicitely asserted by the FPGA to enable the gate drive outputs.
• On your NI general purpose inverter controller (GPIC) mating board, consider routing the high speed digital output gate drive command signals back to the general purpose digital inputs. By reading back  the gate drive command signals, you can detect a failure in the output H-bridge hardware circuitry, which can be detected by the FPGA if the value set to the high speed digital output does not match the value read back on the corresponding digital input channel. Keep in mind that the pulse width of signals read by the general purpose digital input must be at least 7 us.

Question for the developer community-- what other suggestions, tips and tricks or questions do you have related to building high reliability FPGA-based inverter control systems?

[BMac]

Redundant System Reference Design for LabVIEW Real Time, LabVIEW FPGA, and CompactRIO

Redundancy is a common approach to improve the reliability and availability of a system.  Adding redundancy increases the cost and complexity of a system design and with the high reliability of modern electrical and mechanical components, many applications do not need redundancy in order to be successful. However, if the cost of failure is high enough, redundancy may be an attractive option.

This reference design described in this paper provides a framework for building a redundant system using National Instruments Hardware and Software.  To download the source code for this reference design, refer to the files at the end of this Developer Zone article.