Documentation for Zynq in sbRIO-9607

[diegopereze]

Hi everybody,

I'd like to know if there are any documents (manuals, aplication notes, ...) that explain or give indications on how to program the new capabilities that this chip offers: e.g. how to asign process to cores in the arm processor. How to transfer data from FPGA to processor in a deterministic way (faster than the ~50us that could be achieved with the sbRIO-9606 using interrupts).

Any information or documentation that may help the application programmer engineer would be appreciated.

Thanks

Diego

[Bhat_Maanay_Rice]

Hello DiegoPereze,

I'm sorry I do not have the answer to your question, but have a question instead.

What do you mean by "data transfer from FPGA to Processor"? Do you mean data transfer between the RT and the FPGA using the 5 DMA channels available on the 9606? Also how did you come up with the "50us" number? Could you please share the documentation on this with me?

Thanks!

[diegopereze]

Yes, FPGA to RTOS communication.

This document explains pretty well the tradeoffs https://decibel.ni.com/content/docs/DOC-41463

The mecanism I use is the following:

1) FPGA handles acquisition rate. When a new sample is available, the FPGA interrupts the processor (A time critical process)

2) The time critical process reads the sampled data, performs some calculations, and writes back to the FPGA the result.

3) Finally the RT process goes to sleep (wait() primitive) until 1) happens again.

If anyone knows of good documentation, please feel free to post links down below.

Sincerely,

Diego.