ECCE 2012 Poster: A New Platform and Methodology for System-Level Design of Next-Generation FPGA-based Digital SMPS

[BMac]

ECCE 2012 poster PDF attached below.

A New Platform and Methodology for System-Level Design of Next-Generation FPGA-based Digital SMPS

Brian MacCleery¹, Olivier Trescases², Muris Mujagic¹, Damon M. Bohls¹, Oleg Stepanov¹, Garret Fick¹

¹National Instruments, Austin, Texas, USA (www.ni.com/powerdev)

²University of Toronto, 10 King’s College Road, Toronto, ON, M5S 3G4, Canada

ABSTRACT

Increasing adoption of FPGAs for digital switched-mode power supply (SMPS) control is driving interest in improved platforms for design. A new methodology is proposed which includes: (1) A continuous time co-simulation environment, (2) a bidirectional design flow for graphical FPGA programming, simulation and deployment, and (3) a general purpose FPGA based control system suitable for high volume commercial deployment. The feasibility and validity is evaluated through the design of DC-to-AC inverters. User defined FPGA software including I/O is designed without requiring any knowledge of HDL languages. The same graphical tools are used to develop a MHz speed FPGA-based real-time SMPS simulator for exhaustive validation and verification.

REQUIREMENTS FOR SYSTEM LEVEL METHODOLOGY AND PLATFORM

In consultation with researchers and commercial engineers, the application-specific requirements of SMPS designers with regard to system-level FPGA development tools is specified and addressed through significant R&D effort with the introduction of a new commercial platform intended to significantly reduce development cost and risk.

1. The system-level design tool must include a full-featured power electronics circuit simulator that captures the coupled dynamic interaction between FPGA and SMPS
2. The software development flow should be bi-directional rather than unidirectional
3. The FPGA resource utilization efficiency must be comparable to hand written register transfer level (RTL) code
4. The FPGA code used in the final target must be exactly identical to the code used for design validation simulations
5. The tool must include fixed-point math blocks and power electronics IP libraries that enable efficient development of FPGA-based control, signal processing and power analysis algorithms
6. The tool must target pre-validated COTS control boards that meet the specific control, I/O, performance and cost needs of modern high volume commercial SMPS products
7. The tool should be suitable for developing fast, real-time hardware-in-the-loop (HIL) SMPS simulators to enable comprehensive validation of the SMPS control system

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