PWM IP Core with Special Features: Average Current Sample Clock, Rate of Change Limiting, Max/Min Duty Cycle Limits

[BMac]

SUMMARY

• Generates a single channel, left-aligned pulse width modulation (PWM) signal.
• Optimized for use with brushed DC motors, but suitable for other H-bridge applications such as single-phase solar inverters. Use in combination with the "Full Bridge Controller (FPGA).vi" IP core (included with the Cosimulation Design Guide) to generate the four gate command signals for controlling an H-bridge.
• Provides a sample clock signal with a rising edge that occurs at the mid-point of the PWM ON time. As explained below (see the section titled AVERAGE CURRENT SAMPLE CLOCK GENERATION), this can be used to obtain an instantaneous sample that's proportional to the average current. This code could be modified to sample at other arbitrary times during the PWM cycle, as desired.
• Provides a PID clock signal with a rising edge that occurs at a programmable delay before the end of the PWM cycle, as controlled by PID Clock Advance (Ticks). Unlike the sample clock signal, the time interval between PID clocks is always equal to the PWM Period (Ticks). By triggering just before the end of the cycle, your PID control loop can sample the latest current signal and calculate a new PWM Duty Cycle (Ticks) command before the beginning of the next PWM cycle. This provides the minimum latency between the current sampling and the PWM duty cycle response. The duty cycle command is latched only at the beginning of the cycle. By benchmarking your PID control loop, you can determine the appropriate value for PID Clock Advance (Ticks) to ensure that the duty cycle command is updated before the beginning of the cycle.
• Provides PWM Duty Cycle Rate Limiting to reduce in-rush currents in motor/generator control applications. This is particularly useful if the motor/generator is spinning at high speed and the command is reverse. If Rate Limit (Ticks/Cycle) is set to 100, the maximum change in the PWM duty cycle will be limited to 100 Ticks per PWM cycle. This also reduces variations in DC Link voltage caused by changes in the duty cycle command, while still enabling full authority control. Contrast this with a strategy of limiting the maximum duty cycle, which reduces the responsiveness and disturbance rejection characteristics of the control system.
• Testbench application included ("Test VIs (Windows)\Test Pulse Width Modulation, Use in SCTL (Windows).vi"). Includes a digital waveform graph that shows the response of the IP core depending on your control and configuration signals. Run this on LabVIEW for Windows to familiarize yourself with the features of the IP core. If you make changes to the IP Core, you can also use the test bench application to verify your changes before compiling and testing with physical hardware.
• Intended for use inside a LabVIEW FPGA single-cycle timed loop (SCTL) structure containing the digital output I/O node, i.e. for an NI 9401 or NI 9505 module. At a 40 MHz FPGA clock rate, provides 25 nanosecond timing resolution (1 / 2,000th of a 20 kHz PWM cycle, or 0.05% resolution). If higher resolution is required, you can execute the IP core at higher clock rates. Also consider the latency of your I/O module and gate drive circuitry when estimating the overall response with regard to ON Time and OFF Time and your dead-time requirements to eliminate shoot through (which occurs if the upper and lower transistor are closed at the same time.) An external IP Core is used to insert dead-time. For example, dead-time insertion is provided by the "Full Bridge Controller (FPGA).vi" and "Rising edge delay (FPGA).vi" IP cores, both included with the the Cosimulation Design Guide.

AVERAGE CURRENT SAMPLE CLOCK GENERATION

This PWM IP Core generates a "sample clock" output for triggering data acquisition. Use a local variable to read this signal in a separate single-cycle timed loop that waits for the rising edge to occur and then exits, followed by the analog input node placed in a sequence structure to perform sampling after the trigger signal is detected.

In this case, it's designed to give a rising edge at the mid-point of the PWM duty cycle, which is commonly used for sampling the current since it gives a good approximation of the average current. (If the current waveform is triangular, then the mid-point of the triangle and thus the instantaneous value that's equal to the average value occurs half-way through the PWM ON time.) There is a Sample Clock Advance (Ticks) signal that let's you adjust for the time delay between the rising edge and the actual sample clock instant of the C Series module, such as an NI 9215 module.

The sample clock rising edge is always in the middle of the PWM ON time, even as the duty cycle changes.  Note: If you need this functionality in another PWM generation IP core, you could easily steal the part of the code that generates the sample clock and add it to another PWM generation block.

IP CORE DOCUMENTATION

Generates a digital pulse width modulation (PWM) signal. PWM signals are useful for driving loads such as motors and proportional valves because the average voltage supplied is equal to the PWM duty cycle. The PWM DO output of this function can be connected to digital output modules. This function is designed for use in LabVIEW FPGA and is optimized for use with the NI 9505 motor drive module.

OPERATION

At the beginning of each cycle the PWM Duty Cycle (Ticks) input is read and the PWM DO digital output is turned on. The digital output is left on for the amount of time specified by the PWM Duty Cycle (Ticks) input. The cycle repeats when the amount of time specified by the PWM Period (Ticks) has elapsed. The FPGA tick counter is used to calculate elapsed time. By default, one tick is equal to 25 nanoseconds (40 MHz), so a PWM Period (Ticks) of 2,000 results in a 20 kHz PWM signal. The PWM Duty Cycle (Ticks) input is a signed integer, but the sign of the value is ignored. Some applications use the sign of the PWM Duty Cycle (Ticks) signal to determine which direction to drive the motor.

Use the rising edge of the PID Clock signal to trigger your FPGA-based current control PID loop execution. The rising edge of the PID Clock signal occurs just before the end of the PWM cycle. The amount of time before the end of the cycle the edge occurs is determined by the PID Clock Advance (Ticks) signal.

Use the rising edge of the Sample Clock signal to trigger your analog input operation to read the motor current for closed loop control. The Sample Clock signal goes TRUE at the mid-point of the PWM DO output and goes FALSE at the beginning of the PWM cycle. For an inductive load, sampling the current at this time gives a rough estimate of the average current. The Sample Clock signal will continue to be generated even if the duty cycle is 0 or 100 percent. In those cases, the rising edge of the Sample Clock signal occurs at the beginning of the PWM cycle. The Sample Clock Advance (Ticks) signal is used to cause the rising edge to occur slightly before the PWM DO mid-point, to compensate for analog input sampling time. For the NI 9505 module, the analog input sampling occurs 9 FPGA clock ticks after the start of the FPGA I/O Node function.

The Telapsed (Ticks) signal can be used to trigger other operations at particular time in the PWM cycle. For instance, you could use this signal to trigger an analog input operation to occur once per PWM cycle at a programmable time within the PWM cycle. This counter resets back to 0 at the beginning of every PWM cycle.

The Min Period (Ticks) control  is used to limit the PWM Period to prevent switching at frequencies that could damage the output MOSFETs in a digital output device. By default Min Period (Ticks) is set to 1000 ticks, which limits the PWM switching frequency to 40 kHz.

The Duty Limit (Ticks) control is used to limit the minimum ON and OFF time for the PWM output. If the Duty Cycle is less than the limit, it will be coerced to 0%. If the duty cycle is greater than the Period minus the Duty Limit, the Duty Cycle will be coerced to 100%. Some output devices such as the NI 9505 motor drive module require that the ON and OFF time not be less than a certain limit (2.5 microseconds for the NI 9505). By default Duty Limit (Ticks) is set to 100 ticks, or 2.5 microseconds.

The Rate Limit (Ticks/Cycle) control is used to limit the rate of change of the PWM Duty Cycle.  This reduces the current draw on the power supply when the motor is spinning at a fast speed and the duty cycle is changed rapidly, and can be used to prevent the power supply voltage from dipping below the undervoltage limit of the NI 9505 module (below 8 V) and causing the module to generate a fault. The rate limit reduces the acceleration rate of the motor but does not limit peak power output. Alternately, you could use an external capacitor to prevent the power supply voltage from dipping below the undervoltage threshold. NOTE: If you don't need the Rate Limit functionality, you can reduce FPGA gate usage by disabling the functionality via the Diagram Disable Structure on the block diagram.

To obtain the highest timing resolution when using this function in a normal while loop (not a single cycle timed loop), you can perform digital output I/O operations only when the PWM DO value has changed (rather than on every cycle). To do this, wire the Changed? output to the conditional terminal on a case structure and perform the I/O operation when the case is True. If the duty cycle is 0 or 100%, the Changed? output will strobe true once per PWM cycle at the beginning of the cycle. NOTE: The Changed? output only goes true for a single iteration so it should not be used for triggering external loops unless they are single cycle timed loops.

This subVI is reentrant, so you can place multiple instances of the function in a LabVIEW FPGA application and they each will operate independently.

INPUTS

PWM Period (Ticks)- Total width of the pulse (inverse of the "PWM Frequency")

PWM Duty Cycle (Ticks)- Time for which signal output stays True

Min Period (Ticks)- The minimum allowed value for the PWM Period

Duty Limit (Ticks)- The minimum allowed value for the PWM on time and off time

PID Clock Advance (Ticks)- Determines how many clock ticks before the end of the PWM cycle that the PID Clock rising edge occurs

Sample Clock Advance (Ticks)- Determines how many clock ticks before the mid-point of the PWM digital output that the Sample Clock rising edge occurs

OUTPUTS

PWM DO- Digital PWM signal that can be connected to a digital output channel I/O node

PID Clock- clock signal that can be used for synchronizing the execution of a current control PID loop

Sample Clock- clock signal that can be used to trigger an analog input operation to measure the average current in an inductive load

Changed?- Value is True for one iteration when the PWM DO value has changed, or at the beginning of the PWM cycle if the duty cycle is 0 or 100%

Telapsed- The amount of time elapsed during the current PWM cycle

SCALING

The formulas below can be used for scaling from units of Hz, seconds, or percent duty cycle in the real-time host interface application. These formulas assume a 40 MHz (40,000,000 Ticks/sec) FPGA clock rate.

PWM Period (Ticks) = 40,000,000 / PWM Period (Hz)

PWM Period (Ticks) = 40,000,000 * PWM Period (sec)

PWM Duty Cycle (Ticks) = PWM Period (Ticks) * PWM Duty Cycle (%) / 100

PWM Duty Cycle (Ticks) = 40,000,000 * PWM Duty Cycle (sec)