08-16-2018 04:21 PM
All,
We have an application where we take in pulses into the 5646R RF input, do some massaging, and then write them to the output. For us a requirement is to have not just throughput but a minimum latency, that is time delay from receipt of the pulse to emission of the modified pulse.
We wrote a test such that by using dio pins we can trace the timing of the RF pulses as they move through our process. We are surprised to find that there is a 320 ns delay between writing to the RF output and a signal appearing on the output connector. Is this latency in the DAC chip? Anybody know the part number of the DAC chip in the 5646R so that I can look this up? Is there some trick in the FPGA programming that will allow us to speed this up?
Thanks much!
Paul Probert
Sandia National Labs
08-16-2018 06:10 PM
Hey Paul,
I think the latency from the signal exiting the LabVIEW FPGA code to the signal showing up at the output is fixed. I don't think there are any options for speeding that up. You could consider modifying the DSP chain to reduce latency. I'm not an expert on DSP at all, but if you have that expertise, then might be able to create an implementation that is optimized for latency. What is the minimum delay that you can accept? You could connect the ADC inputs directly to the DAC outputs within the FPGA to see what the minimum value that you can achieve is.
08-17-2018 12:35 PM
Sorry, I'm not able to say what the exact requirement is, but obviously trimming down that 320 ns is desireable. I find it hard to believe that the DAC chip alone could have that much latency. I've looked at the data sheets for some chips of similar speed and precision and under a hundred ns seems the norm. I wonder if NI put a little FIFO buffer between the write function and the DAC for some kind of synchronization purpose. If so I was hoping there would be a way to bypass that. I find it disappointing that such information isn't provided in the data sheet.