06-24-2008 05:47 AM
06-24-2008 09:56 AM - edited 06-24-2008 09:58 AM
The 9403, like all other DIO C series modules, does not have a specific trigger or scan clock input that will automatically sample the other DIO lines at a rate specified by an external signal. You can however implement this functionality using the DIO you have and the FPGA. In fact this is the purpose of the Reconfigurable I/O (RIO) architecture. With some basic I/O channels and the configurable hardware of the FPGA, you can define you own custom hardware including triggers, scan clocks, counters, etc.
For your application, sample all of the input lines of interest at the highest rate possible. In the FPGA code monitor your clock line and look for rising (or falling edges). When you see an edge on your clock signal then and only then log all of the data from the other lines into a FIFO or register for processing or to pass back to the host application.
Here's a simple example using a few channels from a 9401 (same as the 9403 but with fewer channels).
06-25-2008 12:06 AM
11-07-2008 01:03 AM
Hi,
Can you please give some insight on aquiring frequency data using 9403??
Thanks
Ajay
11-07-2008 09:22 AM
sharda wrote:Hi,
Can you please give some insight on aquiring frequency data using 9403??
Thanks
Ajay
Can you please be a bit more specific about what it is you would like to do. Also if you have a new questions it is best to start a new topic in the discussion forum, rather than attaching your question to an old thread.
Have you looked in the CompactRIO specific examples installed with NI-RIO?
C:\Program Files\National Instruments\LabVIEW 8.6\examples\CompactRIO
11-12-2008 12:02 AM
hopefully your query has been solved, Javed
Vishal
Applications Engineer
National Instruments
India