Problems readings DATA bits from ADS1675 through DIO on sbRIO9602 (SPI bus)

[Mariano76]

Hello,

i'm trying to read DATA OUT bits from TI ADS1675 ADC through SPI interface.

I've interfaced "DATA OUT", "SCLK" and "DATA READY" on 3 different DIO sbRIO inputs on p4 connector.

i've built a SCTL@ 40Mhz state machine to build a basic SPI reading protocol on FPGA but i cannot see 24 data bits out the ADC despite the fact they are there    because i've checked their presence with oscilloscope.

SCLK out of the ADC is 8Mhz so every bit is 125ns wide and change on every SCLK rising edge.

My state machine consists of these states:

1. look for DREADY going HIGH
2. read DOUT and increment index where i will add next bit on following iteration 
3. look for SCLK rising EDGE
4. wait 1 cycle

basically i do this:

after a DRDY HIGH is detected i look for SCLK rising EDGE (3) and if found i wait 1 SCTL cycle(4) and read out 1 bit (2).

This 24 times. 

I have ARRAY indicator in state 2 where i also update it when i read out 1 bit... 

every bit rising-falling edge is about 3ns so i suppose that waiting 1cycle after SCLK rising edge is detected is enough to read a stabilized value of corresponding DATA OUT bit.. but simply i have some of 24 array elements blinking but no correspondance between word detected through oscilloscope and ARRAY on front panel...

Have you any suggestion or SCTL SPI examples? 

Thanks iin advance

[Mariano76 · Accepted solution]

ok i've found the bug.. simply i haven't placed boolean array on a shift register on SCTL so i was updating and losing sistematically every bit i was updating in the array...

now i can see the correspondance between data bits visualized on oscilloscope and boolean array