Using SIT conection manager with C-RIO

[andredb]

I created one custom VI (name: sitfpga cRIO master teste.vi) in our FPGA environment.

You could see in the picture “project.jpeg” attached.

This Vi are running well, we created it to check the period of one digital signal connect to DI0 port of NI-9423. In the picture “master_running.jpeg” attached you could see the indicator “Periodo (Ticks)” with correct number of period, 1156001.

We use this VI after compiled to create the .lvbit file to use in our application.

If we create now one VI in Windows environment and open the FPGA VI master test, and link one indicator to the indicator Periodo(Ticks) in master teste VI. It works well.

BUT, If I use SIT connection manager to open my Simulink model and make the configurations as you could see in pictures “SIT1.jpeg”, “SIT2.jpeg” and “SIT3.jpeg” I couldn’t get the correct value of period when I execute the VI. See picture “running.jpeg”.

Any one could help me? I don’t know if was clear to explain, if you need any more information to try help me. Fill free to contact-me.

Regards,

[Filipe Silva]

Hi Andre, good morning.

I found some links at ni.com that can help you.

http://digital.ni.com/public.nsf/allkb/4A35E8DB71756E94862572A700755D9E?OpenDocument

http://digital.ni.com/public.nsf/allkb/290DB0EDEAA5547E86256F9D005A145A?OpenDocument

Try to do the steps shown at NI site and let us know all the process.

Regards,

Filipe Silva

[andredb]

Hi, Filipe. We tried both steps and didn´t get any sucess.

We are still in the same point. Do you have any other idea?

Regards,

André Basílio