code size of "set output" nodes

[CyGa]

Hi !
In my application I'm using a 7813R card to send/receive multiple digital waveforms independently. The user set each line to be an output or input, so I'm using "set output" nodes for this configuration. And then to output my data, I'm using "output data" nodes. As my code is taking too much space to fit FPGA possibilities, I analyzed my code to see which parts where taking lots of memory. It appears that it is my subVI containing output/input configuration which is memory consumming ("set output" nodes. ) => when I remove it, memory occupation switch from 99% to 34% ....
Why is that ?

[CyGa]

Nobody ?

[Jared_B]

zyl7,

I will go ahead and look into this and see what I can find out.  What version of LabVIEW are you running?  Additionally, would it be possible for you to post your SubVI or a screenshot of your code so I can understand a little better what exactly you are doing.

[Jared_B]

zyl7,

One possibility (before I see any code) is that your code is still fairly large, even without the I/O, however during synthesis and implementation the tools may be removing unused logic, depending on how your I/O is configured.  This would create the impression that the code is being bloated by the I/O, when in actuality it is just a large amount of code and when the outputs and inputs are removed, the logic is not being used for anything, and therefore not included in the bit file.

[CyGa]

Hi Jared,
You'll find my "configuration" VI attached to this message.
By this method, I want to programmatically control the state of a line (Input or Output) from the host VI (according to 4 boolean values).
If you need the complete project, it's more or less confidential so we'll have to find another way to communicate.

[Jared_B]

zyl7,

I'm still working on coming to a more concrete conclusion on this.  It appears that if the SubVI is compiled alone, it only takes up 1% of the FPGA resources.  Which then leads me to believe that it has something to do with how the SubVI is being used.  Let me do a little more research and testing and I'll post what I find out.

[CyGa]

Thank you Jared.
Indeed, compiled alone this VI only takes up 1% of the FPGA resources... To give you more info, this VI is executed after an interrupt which let the time to the user to enter desired data from the host. When the interrupt is acknowledged, this code is executed and didital signals are sent onto the lines configured in ouput. In a near future (as soon as my resource problem is solved), i'll have to develop a VI which acquires data on the lines set as inouts.

[Jared_B]

zyl7,

I would recommend the following:

1) Using Single Cycle Timed Loops wherever possible
2) Take a subset of the FPGA I/O Methods and make a SubVI, then pass FPGA I/O Constants to it which select different ports and change the SubVI to non-rentrant. This way, there will only be one copy of the SubVI on the FPGA, however, it may slow down the action because of arbitration etc.

Either way, about the subVI using up more slices when it's included in the main VI, I believe the following is the reason.

When you have multiple I/O Methods and Nodes, you always end up creating a certain amount of code for each of it. However, if you start having more than one Method or Node talking to the same I/O Pin, in this case for all the 120 Channels, then extra code has to be brought in to do the arbitration/timing etc. After all, the multiple nodes are talking to the same single pin on the FPGA chip.

Essentially - the more arbitration you have, the larger the code generated for it.

[CyGa]

Thank you for the advices !
I'll try to apply them and let you know if I can better manage my application!

[CyGa]

Hi !
I changed the "set output data" by Constant I/O... Still 99% of the space is occupied...
So it doesn't help a lot... But thank you for your advices !