ni 9871

[kiani123]

Hi, I am using Compact RIO 9022,i want to acquire data using 9871 serial card.

while adding FPGA  I/O method and selecting particular port i.e port 1,2 3 or 4 and method like read or write it does not give furthe option like

data,timeout etc

can any one help me

[WesWNI]

Hello kiani123, 

This was reported to R&D (370152 CAR ID) for further investigation. A possible workaround is to either create this node in LabVIEW 2011, save the VI, and then open this in LabVIEW 2012 or you may open the NI-987x Serial Loopback Example VI from the Example Finder and drag over the method node used for the 9870 and simply configure this for your device/port. Thanks for the feedback!

[MikeP3000]

Kiani,

I came across the same problem.

This solved it for me.

[georgewbush]

THIS IS BAD!!!!!!!!!!!!!!! 

[EthanStern]

This bug is a major drag.  Boooo.  A link to the proper fix would have saved even more wasted time:

http://digital.ni.com/public.nsf/allkb/A1DEA3B97FEE3A1086257A8D005898D7

[Sci-Vi]

Wow... So much time wasted.... And the solution is waiting here for desperate developers...

Wait... Isn't it what can be called a "critical issue" ? You buy LV2012 with RT and FPGA license, buy a cRIO chassis and a Serial module, and the tools you get out of the box for your (tiny amount of ) money are bugged in such a way that it is not usable at all. Not critical ?

What is the NI Update Service here for ??? 3 months after first registering this bug and the oh-so-simple fix (just replace a single file), I would have expected to see this fix proposed in NI Update Service (this is one of the first things we have checked when having this problem, before trying a repair-install of NI-RIO, which obviously did not fix anything but was VERY time consuming too). Sorry but this is quite disappointing.

Vincent

[georgewbush]

Does anyone from NI have any comments? 

[WesWNI]

Hello Sci-Vi,

I apologize for any inconvenience that this bug has caused, however this has been reported to R&D (370152 CAR ID) for further investigation. This CAR has prompted the work around linked below to be created and R&D is currently investigating this issue to be addressed in a future LabVIEW release. We appreciate your feedback!

http://digital.ni.com/public.nsf/allkb/A1DEA3B97FEE3A1086257A8D005898D7  (Why Do NI 987x FPGA I/O Nodes in LabVIEW 2012 and RIO 12.0 Lack Terminals?)

[steve9871]

If I call invoke a Read method for the 9871 with a large timeout, the NI documentation says it will "continue to retry" until the timeout occurs.  My question is, how much of the128Kbytes/sec bandwidth is utilized while waiting for a byte to arrive before the timeout period expires?  i.e. how often the "retry" occur?

Similar question, 

If I run an FPGA while loop with a method that reads the number bytes in the fifo and breaks out once the FIFO is not empty (i.e. # byte >0), how much of the 128Kbytes/sec bandwidth is utilized while we spin in the loop always asking for the number of bytes in the FIFO?

Regards,

Steve

[beccamir]

Steve,

First, it is recommended that you post your question on a new thread as it is unrelated to this one. Also, the community is most likely to give input on newer posts.

Second, are you losing data? Why are you concerned about this? Also, are you referring to the data that is passed between the module and the cRIO?