regular change of frequency and writting data to file

[izabela.p]

Hi!
I would like to change frequency of output signal in every (for example)1s and save data in other file for each frequency.

My vi do it, but saved data is mistaken.Could you tell me, what do I do wrong?

Regards,
Iza

[crossrulz]

You are putting 3 elements into your FIFO every iteration in the FPGA.  Your host code is assuming 1 signal for the actual read.

So your FPGA is sampling at 200kHz.  So in 1 second, you will have 200kHz*3 channels = 600000 elements in your FIFO every second.