sbRIO-9606 vs sbRIO-9605

[kirkscheper]

Dear all,

I am developing a small DIO project with a SBRIO-9606 board and after writing the draft code I am only using about 10% of the FPGA space. I Am only using the ethernet output (not the can or usb ect.). I am however using quite high thoughput speeds on both the DIO inputs and on the ethernet output.The FPGA code is running at 6MHz and the ehternet is spitting out about 60Mbps.

I have to duplicate the design onto two additional systems so my question is, can I safetly downgrade from the 9606 to the 9605 without losing the ability to keep the high throughput rates and FGPA speed? Is there any difference between the boards other than the smaller FPGA and less comms outlets? The downgrade would benifit me as the 9605 is of course cheaper than the 9606.

Thanks in advance for the replies.

Kirk

[kirkscheper]

Dear all,

I am developing a small DIO project with a SBRIO-9606 board and after writing the draft code I am only using about 10% of the FPGA space. I Am only using the ethernet output (not the can or usb ect.). I am however using quite high thoughput speeds on both the DIO inputs and on the ethernet output.The FPGA code is running at 6MHz and the ehternet is spitting out about 60Mbps.

I have to duplicate the design onto two additional systems so my question is, can I safetly downgrade from the 9606 to the 9605 without losing the ability to keep the high throughput rates and FGPA speed? Is there any difference between the boards other than the smaller FPGA and less comms outlets? The downgrade would benifit me as the 9605 is of course cheaper than the 9606.

Thanks in advance for the replies.

Kirk

[srm@viewpointusa.com]

probably.

you can see if your project compiles for 9605 before buying one but throughput will have to be evaluated with real hardware.

[ThiCop]

Hello Kirkscheper,

The differences between the 9505 and 9606 can be found in the following document:

http://www.ni.com/pdf/manuals/373378c.pdf

Some important differences/remarks are:

- Different FPGA's (compilation can be tested)

- same CPU's

- Different amounts of RAM (please check how much you're currently using)

- Same Network Interface
- ...

What are you doing on the LabVIEW Real-Time side?

Is it possible to share some of the code (project, source files,...)?

[kirkscheper]

On the FPGA I am running a custom read only SPI interface in a state machine set up and on the Labview RT I am simply fetching the data from the FPGA, formatting it a bit and sending it off to the user PC over the ethernet LAN.

I will check how much memory I'm corrently using and try compiling the source code for the 9605 and see if it gives me any errors. I will post back here in a week with the results (and source code).

tnx,

Kirk

[ThiCop]

Thanks for the feedback!

I'll see the notification coming in then. 🙂

[kirkscheper]

Hey, sorry for the late reply but here we go. Below is a copy of the summary from both builds, they were both succesfull so I guess it looks like it will work for the 9605 as well. I have attacehed the full Xilinx erport from both builds as well as a copy of the project. The FPGA just reads from 8 ADCs usign a read only SPI bus running at 13.5Mhz (the next version will be at 6.75Mhz to reduce hardware requirements and to meet the NI recommendation of <10MHz SPI).

I would love to get some confirmatino on if you think it will wrok with the 9065.

Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 28.6% (1952 out of 6822)
Slice Registers: 8.4% (4592 out of 54576)
Slice LUTs: 17.0% (4638 out of 27288)
DSP48s: 0.0% (0 out of 58)
Block RAMs: 34.5% (40 out of 116)

Timing
---------------------------
BusClk (Used by non-diagram components): 33.00 MHz (68.22 MHz maximum)
40 MHz Onboard Clock: 40.02 MHz (62.50 MHz maximum)
54MHz: 54.00 MHz (64.73 MHz maximum)

Start Time: 13:05:53
End Time: 13:27:43
Total Time: 00:21:50

Thanks for the help,

Kirk

[kirkscheper]

Sorry, Here is the full summary from both builds

9606
Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 28.6% (1952 out of 6822)
Slice Registers: 8.4% (4592 out of 54576)
Slice LUTs: 17.0% (4638 out of 27288)
DSP48s: 0.0% (0 out of 58)
Block RAMs: 34.5% (40 out of 116)

Timing
---------------------------
BusClk (Used by non-diagram components): 33.00 MHz (68.22 MHz maximum)
40 MHz Onboard Clock: 40.02 MHz (62.50 MHz maximum)
54MHz: 54.00 MHz (64.73 MHz maximum)

Start Time: 13:05:53
End Time: 13:27:43
Total Time: 00:21:50


9605
Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 49.8% (1873 out of 3758)
Slice Registers: 15.3% (4592 out of 30064)
Slice LUTs: 31.0% (4661 out of 15032)
DSP48s: 0.0% (0 out of 38)
Block RAMs: 76.9% (40 out of 52)

Timing
---------------------------
BusClk (Used by non-diagram components): 33.00 MHz (70.47 MHz maximum)
40 MHz Onboard Clock: 40.02 MHz (62.50 MHz maximum)
54MHz: 54.00 MHz (82.52 MHz maximum)

Start Time: 11:27:08
End Time: 11:52:55
Total Time: 00:25:46

[ThiCop]

Hallo Kirk,

Regarding the FPGA side I don't directly see any issue.

Are you planning to go to more than 2 extra implementations in the future?

Have you also checked with the latest compilation and RT code how much CPU and memory (RAM and non-volatile system memory) you're using?

Do you ahve some logs about this?

Thanks in advance! 

[kirkscheper]

At the moment it appears that I am only using about 2.5 MB of ram and less than 1 MB of rom so it looks like I am fine on that as well.

Attached is a quick profile log of the 9606 running the program I attached before.

At the moment the paln is two additional implementations but in teh future it may be more but we may re-evaluate the hardware we use as the sbRIO is a bit more than we really need. We used it now because we know LabVEIW and that makes it really easy for quick development.

I think I will go ahead and but the 9605, thanks a lot for your help!

Kirk

[ThiCop]

One nice thing you could also use to monitor CPU and RAM are RT Disk utilities:

http://zone.ni.com/reference/en-XX/help/370622J-01/lvrtvihelp/rt_board_utilities_vis/