Can you ignore VI Analyzer testing errors?

[croohcifer]

Hello everyone,

I ran into a case where if you put a password-protected VI (the System Exec VI in my case) in a parallel FOR loop, VI Analyzer reports a testing error on the Parallelizable Loops test.  I think this is because VI properties (like reentrancy) can't be queried from password-protected VIs, and the PL test checks for non-reentrant sub VIs in PFLs.  If the VI were mine, I'd add the password to the password cache, but I don't know the password since it's an NI VI.

In general, is there an equivalent to the #via_ignore bookmark or some other mechanism that can ignore VI Analyzer testing errors?  Also, it would be great if NI would have a mechanism for unlocking its own password-protected VIs during VI analysis.  (Maybe this is already a feature?  I'm in LabVIEW 2018, but I didn't see anything along these lines in the VI Analyzer 2019 readme.)

Thanks!

David

[Darren]

A test error means one of two things:

1. A problem with the way the test session is set up (i.e. you have your own password-protected VIs that you're analyzing, but the passwords are not in the cache).

2. A bug in the test functionality itself.

I would suggest that we don't want to ignore either of these two scenarios. And the scenario you describe is a bug with the test itself...it should not try to dig into the diagrams of password-protected subVIs. I have filed myself Bug 953793 to fix this issue. It should be fixed in the LabVIEW 2020 release. And hey, if you had a way to ignore test failures, I may never have found out about this bug at all, so thanks!