The number of bits in packet 1 of Output exceeds 64 bits

[blackburnite]

In my FPGA config file, I have an output packet with 64 boolean elements but get the error NI VeriStand:  The number of bits in packet 1 of Output exceeds 64 bits when attempting to add my FPGA target in the system definition file.

Is there some undocumented bit similar to the late status bit in the input DMA or is this just a VS bug?

[David22JRA]

Hello Blackburnite

when does that error occur? also, can you attach a capture?

Regards

[csparksfly]

There is nothing similar to the late status packet in the output DMA packets. You can find example .fpgaconfig files in the C:\Users\Public\Documents\National Instruments\NI VeriStand 2017\FPGA directory. Any of the files that are the "lines" variant and not the "ports" variant demonstrates that functionality.

One thing I did note is those example FPGA files only have 40 booleans configured for a single packet. Can you reduce the number of boolean elements and see if that resolves the error? Perhaps that will help narrow down troubleshooting efforts.

[blackburnite]

The signals in the DMAs had to change anyways and the error has not occurred since that specific set of signals in the FPGA personality config.  I'm not going to look any further into it for now.