Veristand with DAQ - Trigger line requested could not be reserved error

[Supreeth.K]

Hi,

This post could be more DAQ releated, but I have posted it in veristand as I came across the issue whilst using the DAQ channels in veristand.

Currently evaluating NI Veristand 17 with a simple LV model. I have mapped my inport and outport to DAQ AI and AO respectively. When I try to deploy the SDF I get an error. All details are shown below:

DAQ hardware used (PXI with MXI express PC control):

Veristand SDF overview:

Error Log:

• Start Date: 13/10/2017 12:41
• Loading System Definition file: "I deleted file name"
• Preparing to deploy the System Definition to the targets...
• Compiling the System Definition file...
• Starting VeriStand PC Engines...
• Initializing TCP subsystem...
• Starting TCP Loops...
• Connection established with target LocalPC.
• Sending reset command to all targets...
• Preparing to deploy files to the targets...
• Starting deployment group 1...
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -89126 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> Project Window.lvlib:Connect to System.vi

Possible reason(s):

Trigger line requested could not be reserved because it is already in use.
=========================
NI VeriStand: DAQmx Control Task.vi:3900002<append>
Property: SampClk.OutputTerm
Destination Device: PXI-6225

Task Name: PXI-6225_AI

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Sending reset command to all targets...
• Shutting down VeriStand PC Engines...
• Stopping TCP loops.
Waiting for TCP loops to shut down...
• TCP loops shut down successfully.
• Unloading System Definition file...
• Connection with target LocalPC has been lost.

More details:

* The  file deploys properly when the 'Chassis master HW synchronisation device' is set to none

* PXI_Trig0 is not reserved in MAX

* The same error is seen when I try to export the Dev3/ai/sampleclock to the /Dev3/PXI_Trig0 in LabVIEW

[Riley_Ilieva]

Hi, 

From your screenshots it looks like trigger 0 is used as a sample clock. 

Could you change your LabVIEW example but use trigger one instead of 0 and see whether that works? 

Many Thanks, 

Riley Ilieva

Applications Engineer

National Instruments