Fixed Point QPSK demodulator with MT PSK Example

[pfarrell85]

I am trying to link the MT ni5640R PSK example running on one NI-5640R to the fixed-point QPSK demodulator on another NI-5640R.  Does anyone have any experience with the fixed-point QPSK demodulator?  The requirements for the input sequence data are slightly confusing as to what I need to feed the QPSK demod block on the FPGA.

[Vinay_Kumar]

Hi "pfarrell85",

I have attached a VI which does the QPSK Modulation using the ni5640R instrument drivers.

Sync sequence  to be used is 32 "zeros" and is taken care by the modulation VI.

Note: You will require two IF-RIOs. One for generation using the VI attached, and the other for demodulation using the fixed point IP.

Let me know if you have any issues/ questions.

Regards,

Vinay

[pfarrell]

Hi Vinay,

What settings should I set on the QPSK demodulator for the configurations parameters to work with the QPSK modulator example you provided?  The spec sheet says it should be a root raised cosine filter with alpha between 0.4 and 1.  The QPSK demodulator has many other settings that I'm not sure of.  When I run the demod, it only runs for a second and then stops.  Is there a way to make it run continuously?  Lastly, my constellation for the PLL keeps rotating.  Should this remain constant and look like a QPSK constellation?

Patrick

[Vinay_Kumar]

Hi Patrick,

1. The example for written to run for a few seconds. The reason is that when you are DMA at rates of the order of a few MSamples/s, the host processing might not be able to keep up with the rate. We can try and rearchitect the code, use memory managers in LV and see upto what rate we can sustain continuos DMA.

2. Matched filter coefficients in the host VI has been hardcoded in the Host VI for roll off factor of 0.9 and for root raised cosine filter. So either try using the MT generate filter paramaters and convert to fixed point for a required roll off factor. Or on the modulation sideretain roll off factor as 0.9.

3.Only the ADC decimation factor setting needs to be set properly based on what the symbol rate being used on the modulator side. The Modulation VI gives you what the ADC decimation factor should be on the demodulator side.

4. The constellation should remain constant but phase shifted by 45 degrees, ie. 0, 90,180, 270. If the constellation is rotating, then the ADC decimation setting need to incorrect.

We are working on the next version of the LabVIEW FPGA RF Communcations library. We will definitely consider your feedback and improve the examples and the IP.

--Vinay