How to determine FPGA code size ?

[CyGa]

Hi!
Designing my application, I would like to have an estimation of the memory space it will take into the FPGA ... Is that possible ?

[Vinay_Kumar]

Hi Zyl7,

I guess you are talking about the amount of logic gates/ slices used by the code on the FPGA. AT present, LV does not estimate this number.
This number is based on the clock rate at which you want the code to execute. You will have to compile the code and look at the Device utilization summary provided by Xilinx.
If you have already compiled the code, you can right-click on the FPGA VI in the project window and select "Target specific properties".

Number of Slices correspond to the amount of logic occupied by the code on the FPGA.
Number of RAM16s corresponds to the amount of memory blocks being used by the code.

[CyGa]

Hi,
Thank you for this detailed answer. So if understand well, I have no way to know if the code I'm developping can be stored in the FPGA before compiling...
If the compiling time was short, it would be no problem... but i'm not imagining myself compliling 100 hundreds time my code to see memory/slice utilization differences...

[Vinay_Kumar]

Yes I agree with you. Here are some tips that might help you during coding.
1. Avoid using series of multipliers.
2. Avoid using too many nested case structures.
3. Avoid using replacing more than one element of an array at a time.
4. Try and pipeline your code as much as possible to achieve higer clock rates.
5. Identify the critical path and see if you can reduce this length by adding register in between sections of the code.
6. After all this, do not forget to test the functionality of the code on your PC before starting the compilation process.

All the above are applicable when you are writing code inside a single cycle time-loop.

I would also recommend that, do compile your code in parts rather the complete system. In the meantime, you can disconnect the compile server from LV and continue work on other sections of the code. After the compilation is done, you can always reconnect to the compile server to link the bitfile to the VI.

You will learn to estimate the clock rate and slices used on the FPGA.

--Vinay

[CyGa]

Alright ! thank you for the advices !

[Peio]

Hi everybody,

I'm agree with you, compiling sub-VIs instead of entire target VI is quite a good idea, BUT, how can I do it if I'm using FIFOs?

I can't compile my code if I compile my target VI by parts containing FIFOs read node. Is there anybody in the same case?

Pierre

[Vinay_Kumar]

Hi Pierre,

Instead of compiling sub VI by sub VI, compiling one module of the code which does not share any FIFO across modules would make sense.
Ideally, I would not recommend you to use Target to Host and Host to Target FIFO within sub VIs as the portability of the code/sub VI becomes difficult, ie if someone else wants to use that sub VI / IP the user will have to create a fifo with the same name in the project, which is not a good coding style.

Good question!

-Vinay


Message Edited by Vinay Kumar on 05-21-2008 05:42 AM