Power Electronics Development Center
Tutorial Presentation: FPGA-based Real-Time Simulation of Power Electronics: Challenges & Solutions
Hi Vijay!
Thanks for your note. Great comments- I apologize for being so slow to reply. The new year has been a whirlwind. I hope it's a good sign of an improving economy.
Regarding FPGA versus DSP, I think there is growing consensus in the industry that FPGA-based real-time simulation is the technological winner. Even with high end processors or GPUs, bus latency typically puts a hard speed limit at about 10 us (100 kHz). In theory, DSPs could be faster (than processors) assuming no bus between the processing cores and I/O, but it can be a challenge. True parallelism of an FPGA and the fast pin-to-pin times are unbeatable. It feels to me like industry consensus is converging on FPGAs as the solution, and the DSP core counts are going up with Moore's Law, which, because of it's exponential nature, becomes increasingly impactful in the next few years. (The rate of MMAC performance improvement is proportional to the MMAC performance itself.) However, harnessing the parallel processing capabilies of large FPGAs is a real challenge using text based programming languages. LabVIEW is a more natural model of computation since it's always embraced the concept of multiple, parallel tasks executing in parallel. So, LabVIEW maps beautifully to FPGAs, arguably more naturally than it maps to processors (at least single core ones).
Regarding your queries...
1. The accuracy of the fixed point model can be very high. It really depends on how you map to the fixed point word lengths, which depends on the component values you have (max and min R,L,C for example) and how you do the matrix scaling/normalization. To get a feel for this, run the VI in the reference design titled "Verify Fixed Point Matrix Normalization Scaling." Pick some scaling values (Vo, Io), then click "Run Sim". At the end of the simulation, you will have three error values representing the difference between the floating point simulation results and the fixed point (FPGA) simulation. You will see that different scaling values will impact the amount of fixed point error.
I am working on updating this example to improve the way the matrix normalization scaling is done. This will give you three scaling parameters to use and enable you to scale every value in the state-space matrix. I also made a version of the state-space for the case in which the load inductance is zero. If you set Lload=0, it uses the alternative flavor of the A matrix. I still have some work to do in cleaning this up and documenting how the normalization scaling is done, but if anyone needs this sooner rather than later, I can post it as is, and then finish cleaning it up later.
2. Yes, you can absolutely integrate this into Veristand by creating a custom device. However, keep in mind that the communication with Veristand is typically single-point rather than waveforms, so you may need an alternative communication mechanism such as LabVIEW Simple Messaging (STM) to stream the waveforms from the Multicore cRIO or PXIe RT system to the host computer. I'll ask our Veristand gurus to comment on this.
3. Yes, FPGA is really the ultimate solution, with clear technical advantages in terms of speed over a processor. Yesterday I updated the PDF with a chart from Prof. Iravani that shows the simulation accuracy for a 2 kHz and 8 kHz PWM switching carrier frequency on the inverter relative to the simulation speed. In the updated PDF, this is slide 46. On a processor based simulator, you typically start to hit a real wall at around a 10 uS. The problem is not so much the speed of the processor but the latencies involved, responding to the interrupts, transfering data back and forth, memory read/writes/queuing, etc. For an 8 kHz inverter, that's about 9% error, which is really significant. You really want sub-microsecond rates for your real-time simulator, which FPGAs can easily provide.
