According to LabVIEW FPGA 2018 Help, "Using a sequence structure inside a single-cycle Timed Loop has no sequencing effect."
The compile should fail when these structures are used inside single-cycle Timed Loops.
NI's own example of guaranteeing sequential access to a shared resource shows a flat sequence structure, with no note or caveat about using the structure inside SCTL.
-Steve K
