Best architecture for cRIO implementation

[Harss]

Hello,

I need to fix an architecture for the implementation on cRIO.

My current operation involves

1:Flushing out elements from the FPGA to RT DMA FIFO when the number of elements remaining in the FIFO are approximately 60,000

2:My  second loop on the cRIO does processing of each element using a For loop and when the number of elements satisfying the processing criteria are greater than or equal to ten I need to transmit it using Network Streams . This is my current requirement.

3:I am using Queue to transmit buffered data from the first loop to the second loop.

My observation:

1:The first loop executes pretty quickly while the second loop involves processing and is a lot slower compared to the first loop . As a result, I am able to transmit very few data points on my PC after which the VI on the cRIO stops automatically.

I guess the reason for such a kind of behaviour is probably the Queue is filling up much faster than it is getting emptied due to the slow processing speed.

I need an efficient Architecture which  handles such kind of memory constraints. Could anyone please propose an efficient Architecture for handling this?

Thanks.

[Sam_Sharp]

Why are you waiting for there to be 60,000 elements before reading them? Why not read all the elements that are available each iteration of the RT DMA FIFO loop?

In any sort of producer/consumer architecture, you normally expect to be producing lots of data very quickly in the producer loop and then you buffer it in a queue to the consumer loop. Generally the consumer loop runs much slower (e.g. writing to a file) so you have to either accept that, or find a way of reducing the time it takes to process the consumer loop (e.g. data reduction).

[Harss]

Hello,

Thanks a lot for the response . I tried to reduce the speed of the producer loop by using a Wait For Time. However, using this did not solve the issue as using a wait for longer time causes the FPGA to RT FIFO to fill up completly and get Time Outs.

Any possible hints on using Circular Buffer or any other architecture would be really helpful. I cannot reduce the number of data points as it is the requirement.

Thanks.

[crossrulz]

What kind of processing are you doing?  Could you do that processing in the FPGA?  If so, that would be A LOT more efficient.  Then you only send the data up to the RT (and then straight to the Network Stream) when you find the desired condition.  Since the FPGA is just hardware, you don't have to worry about memory filling up.  You just have to worry about how much fabric you are using.  But you will know that at compile time instead of run-time.

[Harss]

Hello,

Its a sort of chunk processing wherein I need to process the data in the form of an array and determine if samples have value greater than the threshold .

1:In case there are successive samples greater than threshold and the array size of these valid data chunks is greater than 10 (say for example i.e. number of successive samples having their values greater than threshold is more than 10) then I need to find the peak amongst these valid array chunk.

2:I then accordingly transmit the entire valid chunk(10 or more successive elements greater than threshold)along with the timestamp for the peak value within that valid data chunk.

This is just a part of processing, but there is a huge algorithm like number of zero crossings and all these algorithms need to be applied on the data chunks in a stepwise manner to determine the valid data and then finally transmit it.

Its fairly a huge volume of procesing and further implementing it in the form of Arrays on the FPGA seems to be a bit challenging to me.

Any further inputs on this would be really appreciated.

Thanks a lot.

[crossrulz]

Everything you mentioned could be mostly implemented on a point-by-point basis.  At least do these ones in the FPGA.

[Harss]

Hi,

I will give it a try on the FPGA, for at least the thresholding part ,but am not sure if all the processing could be done on the FPGA . I wil keep this post updated on my progress.

Thanks once again.

[Harss]

Hello,

I tried this today , unfortunately I was unable to get it right. I was unable to compile the code as it always gave an error 

"LabVIEW cannot determine the size of the array output because arrays of different sizes are wired to the node. Ensure that all array inputs resolve to the same size.

Call chain:
Acquisition_FPGAmain.vi"

And the error points were the Shift Registers and the Case structure nodes used in the VI. I searched about this on various forums and didnt get any clue . I tried writting a very simple code individually on a seperate FPGA VI unfortunately it also did not work.

It would be really helpful if anyone could tell me how to handle the shift registers and Case Structures on the FPGA VI as I am unable to understand the issue completly.

Please find attached a small snippet of code which too was unable to compile successfully.

Please note : I have set the fixed size of array for the Array constant it still does not work

[crossrulz · Accepted solution]

Right-click on the array constant to the left.  There should be an option to set the array size.  Also, remember that arrays in an FPGA must be a fixed size.  Therefore you need to use Replace Array Subset instead of Build Array.

[Harss]

Hi,

Thanks a lot for the feedback . I will try this and keep the post updated.

Thanks