CPU usage hits 100% during FIFO read

[Prashant_dsp]

I have a real time PC with a 7833R RIO board. I write values which I read from a microphone into a FIFO at a sampling rate of 4 kHz.The length of the FIFO is 2048. On the real time PC, when I call "FIFO read" function to read say 400 samples of data, the CPU utilization of the real time PC hits 100%. Why is this so? The "FIFO read" function is placed inside a while loop.

Thanks

Prashant

[jareds · Accepted solution]

Hi Prashant,

The FIFO Read is a polling method, so if the number of element specified to read aren't available when the method is called, it will poll the FPGA until they are.  This causes the CPU to reach 100% usage. You can find more information about this and a way around this here.

[H_SH]

Hello Prashant,

Jaared had given good link to work on.. I suggest about time syncronisation on FIFO read and write..

Consider following case:

B is the data written to the FIFO at F1 frequency and read at F2 frequency

 
then, time taken to write to the FIFO = B/F1 ;

data read from the FIFO in this time=(B/F1)* F2;

If F1>F2 (write freq>read freq)

The Excess data remained unread = B- (B/F1)* F2;

If F2>F1 (read freq>write freq)

The lack of data for syncronisation = (B/F1)* F2 -B;

The above can help you in designing of synchronised FIFO

Apart from that please use time out also based on above calculation with time

BR, HS

[Prashant_dsp]

Hello HS,

Your post makes a lot of sense. My read and write happen at the same sampling frequency. So this should be easy. Thanks!