Call Multiple FPGA VI from a Non-FPGA VI

[RRI_user]

I am using NI PXIe-1062Q Chasis (connected to a Dell workstation Precision 1700) with the following modules :

1. NI PXIe-8381

2. NI PXI 7851 R

3. NI PXIe-6738

4. NI PXIe-6535

In my workstation, I have plugged in the PCIe-8381 module for connecting NI PXIe-8381 to the computer into a PCI-E Gen 3 x16 slot. Now here are my questions :

Q.1. I am trying to control three FPGA sub-VIs from a Non-FPGA Top level VI. I have attached all the VIs. The FPGA VIs do the following:

In one FPGA VI, I switch ON a TTL signal in one DIO channel of Connector 0 of 7851R

In second FPGA VI, I set a wait time

In third FPGA VI,  I switch OFF the TTL signal in that channel.

I want to generate a TTL pulse as I had posted earlier in this post which was successfully done. However, here the difference is that for all three elementary actions: switch ON, WAIT and switch OFF, I have separate VIs. When I call these VIs in sequence using FPGA references, I do not get the desired result. I set the wait time to 1 μs, so I expect to see a 1 μs TTL pulse. However, I always (even if I set WAIT time 1 second) see a 250 μs (with a jitter of 750 μs when running continuously) ON time followed by a non-linear decay on my oscilloscope. I could precisely control the timing getting a very nice TTL pulse when all three actions were in one FPGA VI (as explained in the linked post above). Now I need to separate them into three files. But it is not working as expected.

Q.2. This is related to the behaviour of different FPGA VIs. Suppose, I make two FPGA VIs: One to I switch ON a TTL signal in one DIO channel and another to I switch ON a TTL signal in any other DIO channel. If I run the VIs directly one after the other (without calling from any host) then if the first VI turn one channel ON, the second VI will turn its own channel ON but will also turn off the channel which other VI had turned ON. In fact, the contents of the second VI don't matter. Even if it's a simple WAIT VI it will turn off the channel which first VI had switched ON. This may be related to my Q.1. because I have a wait VI after Switch ON VI which might be turning off the TTL in the channel. But this work should only be done by OFF FPGA VI.

I am looking forward to suggestions.

Below are the screenshots of all VIs :OFF VI

ON VI

Wait VI

Non_FPGA Host VI

[Terry_ALE · Accepted solution]

1. The whole point of an FPGA is to give it a task to do and not have to go back and forth between the PC and FPGA.  This delay is never deterministic and your TTL pulse will always vary.

2. Your FPGA VIs need to be one.  When you close/open the reference, the FPGA (depending on config) is getting reset.

3. Review documentation on Host to FPGA interfacing and review examples for your hardware.

[RRI_user]

Hi Terry_ALE,
Thanks for your suggestions. I have tried to modify my VIs as described in my new post here.
1.Now I use case structure and DMA FIFO to accomplish the task.
2.Thanks for pointing this out. I unchecked the "Close and reset" option in the Close FPGA VI Reference method. It resolved the issue in my case structure method. Not sure whether it works when an FPGA VI calls different FPGA SubVIs.
3.I will keep on learning by reviewing a variety of references and with the support of fantastic NI online community.

Please read my new post for the issue I am facing now.

[wiebe@CARYA]

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@RRI_user wrote:

3) ...with the support of fantastic NI online community.

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As you are done with this thread, would you consider marking a (e.g. Terry's post as) solution? It will prevent the online community to keep opening this thread, trying to help as it is unanswered. TIA.

[RRI_user]

Yes.

[wiebe@CARYA]

kudo.