FPGA Compilation error advice - Internal Name

[blue_cortina]

Hi

When trying to compile the LV FPGA code I get a timing Violation error for "Non-diagram component" with internal names such as:        "/G2X8ChinchWithDmaPortBim128x/Gen2X8_Kintex7XilinxCoreDmaPortInternalx/ChinchCore2X/ChinchStatusPusherX/IspIf.LowerStatusBuffer/Kintex7Gen.TheK7Mem/IspIf.sIntStatHeader[4]_i_3/O."

LV does not trace this back to the block diagram and won't show me the element causing the problem. Are there any techniques people can suggest to use for tracking down the route cause? Is there a way of using this internal name??

Thanks......

[MariusU]

Hi,

Unfortunately, from my experience and from all the resources I read, this error usually doesn't point at a specific bits of code on the block diagram. This is because you get this error when the compiler simply cannot satisfy the timming requirements you specified in your code. So for example, the compiler could not allocate enough resources to make sure your code executes in the time you specified.

You can think about the compiler as a city planner trying to draw the shortest-path road between thousands of points and making sure that everyone has the same transit time. So even if the compiler knows that the timming is wrong between A and B, even by a little - it cannot easily figure which exact bit of code you should change for it to be able to meet the timming requirements.

One thing we can do to reduce the number of paths the compiler is routing is to remove the implicit enable signals from SCTLs.
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_routing_congestion/

Other options are to try and reduce the amount of gates used by trying to find and replace redundant bits of code if there are any. If you are using the FPGA in Hybrid mode, consider does it need to be used in Hybrid mode? As that takes up additional resources on the FPGA for the Scan Interface. 

Reducing FIFO sizes or numbers if possible is another way of reducing gates used, data representation size as well. Even un-wrapping subVIs would give the compiler more gates to work with.

The main point is that the code can probably be optimized in some way to allow the compiler to meet the timming requirements, so any adjustments that you might can help.

Kind Regards,