FPGA DMA timing

[boileroo]

Hi all

I would just like to confirm that my understanding of DMA transfers is thus far correct, and then ask a couple of hopefully simple follow up questions!

I wish to sample 8 analog inputs (PXI chassis) at a rate of 500kHz. I have an FPGA loop running at a period of 2 usec (1/500k), equivalent to 80 ticks (40M/500k=80).

My RT host, having openeed the FPGA and FIFO reference then proceeds to run a loop with a period of 10ms. To keep the FIFO from overflowing I am withdrawing 40,000 elements with each iteration of 10ms host loop. This equates to 4M samples per, second, which is accounts for the 500k samples per channel (5k*8=4M).

I have the FPGA FIFO size set to 8191 elements; I was unsure on how to size this parameter and so this is an arbitrary figure! Any insight on sizing this better would be appreciated. The same goes for sizing the depth of the host FIFO please.

Is this the best way of doing things, or have I completely misunderstood somthing here?!

The last piece of advice I would like is regarding timeout values for the FPGA loop and the RT host loop; currently they are both set to zero as again I was unsure how they should best be adressed.

Many thanks for your help!

[Larry.C]

Hi Boileroo,

I think you are doing fine with the sizing of the FIFO. There is no 1 equation that will calculate what the best FIFO size is, it is down to how safe you want the FIFO to be. All you are accounting for is those situations where the RT side is a few ticks late here and there when trying to extract the FIFO data meaining you have space for the next. If it was up to me I would set the FIFO to as big as it goes on the your FPGA since doing so will not effect the performance of the FPGA.

With regards to the timeout, this specifies the maximum amount of time a Timed Loop can wait to begin execution. The default is -1,which means that no timeout is specified for the next frame. The timeout value is relative to the start of the Timed Loop or the end of the previous iteration and is specified in units of the frame timing source.

Kind Regards,

[nathand]

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boileroo wrote:

I have the FPGA FIFO size set to 8191 elements; I was unsure on how to size this parameter and so this is an arbitrary figure! Any insight on sizing this better would be appreciated. The same goes for sizing the depth of the host FIFO please.

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Generally you want the FIFO on the host side to be much larger than on the FPGA side, because there is much more memory available on the host and the host can read many points out of the FIFO in a single call. As you might be aware, when you write to the FIFO on the FPGA side, those values get copied into the FPGA buffer. Periodically - I'm not sure of the exact mechanism - that buffer is copied into the host buffer, and the FPGA memory is then free for the next set of values. There is little harm in making the host-side buffer too large. Of course you always need to read at least as fast as you write, but a larger host buffer lets you read more points less often.

[Intaris]

I think you'll be surprised how small you can actually make the FIFO on the FPGA side.  The data gets swept away pretty quickly.  I was implementing an Oscilloscope (1MS/s 32-bit) and only ever had maximum 3-4 elements in the queue because the background transfer was quite efficient.  I had originally thought I'd need 8000 elements, but settled on 8.

You can read how many slots in the FIFO you have left when writing.  Monitor this over time (Write the value to a FP control) or simply monitor the maximum number of elements in the FIFO over time.  Then set your FIFO size a little bigger than that.

If your RT won't read fast enough, making the FIFO on the FPGA bigger won't solve your problems.  It'd be like using a SECOND fly-swatter in order to take down the death star......

Shane.