FPGA DRAM maximum number of request before retreive data

[Guillaume_B]

Hi,

I have a question about DRAM. Concept of DRAM are not a problem for me.

I have 100k U32 words to record in memory and i need them to replay later.

My idea is to request all element in a first time and then start replaying it with handshaking command on retreive node.

So my question is how many request can i do consecutively before starting to retreiving it ?

Thank you for answer.

Regards

[Jacobson-ni]

The requests and retrieve can happen in parallel. You can change how many outstanding requests you are limited to (I think it defaults to 64) but in the simplest case you just loop the ready for input of the request node back onto itself so you don't make a new request unless it's ready.

In parallel you can always be trying to retrieve data and just not do anything unless the output is valid.

You may also want to consider using the DRAM FIFO IDL but either way there are some examples under Hardware Input and Output > FlexRIO > External Memory in the example finder. The getting started example shows off the IDL but the memory integrity test does a better job at showing off the basic nodes.

[guillaume-arcale]

Thank you matt for your answer !

You are right but in my case, the maximum outstanding request is 512 and i need 1024 so i use target scoped FIFO to do the job.

Regards

Guillaume