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[LVFPGA] Maximum number of DRAM Memories per bank

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Hey there,

 

I've been trying to compile a fairly large LabVIEW FPGA project (which I can't post) running on a 7822R board (PCIe and PXIe). By design I need to use 32 DRAM Memories (each memory independently stores local data for one physical channel). But when trying to access more than 16 memories in the code, the synthesis fails (after about 15-20 minutes of compilation). Attached is an example of the Xilinx log when trying to compile with 24 DRAM memories.

 

- Vivado 15.4 & LV FPGA 2017

- Tried setting the Maximum of Outstanding requests in the memories properties

- Tried changing the Grant Time of the memories in the FPGA target properties

- Tried refactoring the code (the DRAM Write were originally sitting inside a [ugly] 32-cases case structure) to get a flat/parallel layout. Despite what the Xilinx log says (ERROR: [Synth 8-97] array index 23 out of range [/opt/apps/NIFPGA/jobs2/rZ21601_M8wQuBM/PkgDramBank0.vhd:47]), the DRAM memories are not accessed in an array-like fashion.

 

I could not find any documentation relative to the DRAM that mentions a maximum number of memories instances. Have I missed a document? @NI, is that something expected?

Eric M. - Senior Software Engineer
Certified LabVIEW Architect - Certified LabVIEW Embedded Systems Developer - Certified LabWindows™/CVI Developer
Neosoft Technologies inc.

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Accepted by topic author Eric.M

From experience, I remember the limit being 16 partitions per DRAM bank.

 

I can't speak to the reasons why that is the limit but I remember we filed CAR 598399 in hopes that the error could be caught during intermediate file generation and a more clear reason given to the user.

Matt J | National Instruments | CLA
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Hey Matt,

 

I'm kinda relieved that this is a "known" behavior/limit...

I guess the very first thing to do would be to document that limit somewhere in a KB on in the help... Alternatively, preventing the user from creating more than 16 DRAM memories per bank or, as you suggested, report it in the intermediate code generation.

 

Are you able to tell me what the current status on the CAR in nippm (mostly out of curiosity)?

 

Thanks!

--Eric

 

Eric M. - Senior Software Engineer
Certified LabVIEW Architect - Certified LabVIEW Embedded Systems Developer - Certified LabWindows™/CVI Developer
Neosoft Technologies inc.

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@Eric.M wrote:

 

 

Are you able to tell me what the current status on the CAR in nippm (mostly out of curiosity)? 


Can only tell you that it's not currently fixed, sorry.

 

I linked the CAR to this forum so they know more people are running into the issue though.

Matt J | National Instruments | CLA
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