I have most of my LabVIEW FPGA experience with Xilinx ISE compilations. When doing these compilations, pretty much ALL clocks defined in the system showed up int he timing report of the compilation. But now, using Vivado, our CLIP clocks (which runs practically ALL of the code on our target) does not show up in estimated or final timings at all.
What do we need to do to make these clocks appear in the compilation results?
The clocks are constrained, it will fail on a timing violation if we push it too hard. LabVIEW must be deciding on which clocks to report ona nd which not to report on.... how to add our custom CLIP clocks to this list?
