I have some VHDL IP that I am trying to load/convert to clips for a PXIe-6592. When I try to load some of it and check syntax in LV I'm getting..
The following port in the top-level synthesis entity has a type that is not supported. The supported port types are "std_logic" and "std_logic_vector".
Does this really mean I need to go through the VHDL code and re-structure all the code so that the ports are not of boolean or integer range type? Is there a work around for this? The code was written for a virtex-5 FPGA it should be able to be moved over pretty easily to the kintex-7 on the 6529, bool and int range should be accepted i would think.
