Looking for a detailed description of the use of PXI-to-FPGA DMA

[saxegaard]

Hi, Im currently developing a PXI/FPGA based controll system, using the FPGA for input/output, and the PXI for calculation and data processing. I've successfully implemented data transfer from FPGA (target) to PXI (host) using the DMA FIFO structure. However, with the new version 8.2 of the FPGA package, DMA transfer from target to host have also become available, and I would like to use it.

Do anyone have any experience with this? How does e.g. the array size of the input to the DMA.write function related to the DMA depth? I would greatly appreciate any comments, suggestions or links

-saxegaard

[Oli_Wachno]

Hi saxegaard,

I've been using FPGA DMA FIFOs in both directions (though under RT). Didn't have major problems so far.

I don't understand your questions about the relationship between array size and FIFO depth. The way I understood that whole topic ist that the user defines (allocates) DMA memory segments on the host which can be accessed from the FPGA. This determines the maximum size of the array you can write into it at once without the other side taking elements from the FIFO. If I remember it right, the FIFO write returns the number of available elements. This can be used for keeping the FIFO full or respectively transferrring an amount of data that  actually exceeds FIFO size.

Hope that helps

Oli

[saxegaard]

Thanks for your answer. I found another way to implement the host-to-target data transfer, but still- good to know for the future 🙂