Open FPGA References change to No Target when compiled into real-time startup executable

[jmorris]

Hello again you helpful forum-goers!  I have a problem that I am hoping someone can give me a hand with.

I have a project which has a Windows component and a real-time target component, both of which are running on a Hypervisor PXI 8110 system.  The two sides communication with each other using shared variables. 

On the real-time side, I have four FPGA targets which are reading and writing various analog and discrete inputs and outputs.  I have multiple timed loops which open a reference to one of the FPGA targets on the first call, then pass that reference into multiple subVIs which read and write to the FPGAs' front panels.  The loops keep the FPGA reference open and reuse it in the next iteration via shift registers.  Each FPGA target has only one reference opened to it.  One of the loops uses the FPGA reference directly and does not pass it into any subVIs.

All of this works great in the development environment, I can read from and control the FPGA inputs and outputs via the front panel of the Windows side application.  It also works fine if I run the real-time side in the development environment and run the windows code as a stand-alone executable.

However, when I compile the real-time code into a startup executable and deploy it to the target, it does not run.  I have enabled debugging on the executable, and when I connect to it via the Operate -> Debug Executable menu option, I see a broken run arrow.  Further investigation shows that each of the four Open FPGA Reference VIs is now blank, the accompanying text underneath them is "No Target", and the reference wire from them to my first subVI is broken.  I need your help to figure out how to get it to work like it does in the development environment.

I have followed the instructions in these two knowledge base articles to compile and download the FPGA bitfiles onto the FPGA targets and have them run on reboot or startup:

http://digital.ni.com/public.nsf/allkb/39795847AC67296D862575FB0046944F

http://digital.ni.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument

The Open FPGA Reference VIs are configured to correspond to the FPGA Build Specifications that I have created for each of the FPGA targets in the LabVIEW project.

I have called NI phone tech support and they have not yet been able to figure this one out, so extra brownie points if you do!    I would provide you the same non-detailed screenshot that I did them (I cannot give more detailed code out because it is proprietary, unfortunately), but apparently the forum doesn't like my image file, as I cannot get it to load.

Please let me know if you have any ideas as to what is going on!  I appreciate it. 

[GregFreeman]

Save your image as a png then try to upload it again.

[jmorris]

Thanks!  I wasn't able to get it under the 1MB size limit to insert as a picture (PNG being 3 times the size of the JPG), but see attached.  Sorry, image manipulation is not my expertise. 

[Edited to replace with non-cropped picture, since it didn't make it less than 1MB anyway]

[GregFreeman]

Very nice code. Have you tried connecting up the resource name to see if that makes a difference?

[jmorris]

Thank you! 

If you mean a purple constant like "RIO1" to the input of the Open FPGA Reference VI, then yes I have tried that, and it did not make a difference.  If it helps, when I did that the real-time executable version showed a coercion dot connecting the constant to the Open FPGA Reference VI.  I'm not sure what that means, though, if anything.

[GregFreeman]

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@jmorris wrote:

If you mean a purple constant like "RIO1"

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Yup, that's it.

That's very strange. I have never had this happen, and NI obviously has more resources to troubleshoot it than I do, so I'm going to go ahead and say I'm stumped.

[jmorris]

Now I'm wondering if I shouldn't have mentioned that I've talked to NI tech support.  I wouldn't want people to give up prematurely because they think they can't possibly come up with something that tech support didn't! 

[ZachAttack · Accepted solution]

Jon,

I'm still up for the challenge.  Have you tryied recompiling the FPGA VI that the RT VI is accessing?  I would also suggest trying to open the bitfile instead of the FPGA VI.  Are you running in dynamic mode (this is not a suggestion, but just a question)? Is there any difference if you try opening the FPGA VI reference outside the while loop, then pass the reference to be used inside the while loop without shift-registers, then closing the reference to the FPGA VI outside the while loop? 

Let me know if these suggestions make any difference.

[jmorris]

Zach,

I did recompile the FPGA VI multiple times without effect.  Opening the reference outside the loop and closing it afterwards did not help either.  Three of my references is running in dynamic mode, and one is not in order to allow referencing a typedef.

However, changing the configuration of the Open FPGA Reference VIs to reference a bitfile instead of the VI or FPGA Build Specification (both of which I tried) did in fact fix the problem!  I had to add the necessary resource name input as well, but that was easy.  All of my open reference VIs now look normal when I debug the remote application.  The overall application still doesn't work, but that's going to be a separate post. 

Thanks for your help!

-Joe