PLL FPGA (Sine Wave generator, PID and Mod function)

[ESturov]

Good day.

Mainly I work with Matlab/Simulink software and now I am designing a modified PLL system. I’ve implemented this block in Labview 2014 with the Control and Simulation module without any issues. However in a couple of weeks this code should be ran on cRIO 9068 FPGA, so now I am trying to convert my codes to the FPGA code. I have some experience in FPGA programming in terms of the control of analogue inputs/outputs, but this PLL design is something totally new for me.

I’ve designed the code in FXP (I did the same code in SGL before but then decided to focus on the FXP version). The Simulink representation is presented in the message as well. I am trying to evaluate the performance of the system by using three sine wave generators (A, B and C phases).

1. What is it about the Amplitude values? Because in my case it shows 127.5, I assume 2^7, but why exactly this value and not 128? Or 256 – 2^8?
2. PID FPGA – the output is zero. More or less I figured out how to use the gain values, but more confused with a setpoint input. Because in Control Theory a step signal is used to tune a PID controller, and this is the way how I do it in Simulink as well. However in case of the FPGA code I assume I need to put a real targeted value?
3. Why the limits by default are 2^15?
4. The sampling time – 1 s by default. The most confusing since I can reduce it to 10 ms, but can the PID work faster? Or I just don’t understand something here and there is no need to do it?
5. Quotient and Remainder that does not work here. But I found another topic where I’ve the suggestion to use a while loop (please see the attached model). Are there any other options, or this one will do?

I know that most of these questions are quite basic, but I really need to understand the processes in the model before run it in real life. Thank you in advance.

[stockson]

Hi,

I will try to answer at least some of your questions:

1) I'm pretty sure they mean peak amplitude. So 2^8/2.

2) I'm not sure if I understand correctly, but I believe the answer is yes - on FPGA you are designing an application that will be controlling some plant, so you need a real signal.

3) Limits of what?

4) Is there a reason you are using an Express VI instead of the regular FPGA PID block?

5) If it works I'd leave it as it is 🙂 Division is a problematic topic on FPGA.

[ESturov]

stockson,

Thank you so much for your quick response. 

1. Ok, sounds reasonable, at least so far 

2. Yeah, I think I forgot about a sentence or two, sorry about it. When you use a step signal to check the system's response, your output is obviously one. That's how you can tune your PID without even knowing a value of the output signal (again, talking from the Control Theory perspective, maybe I am completely wrong in terms of FPGA coding). The same here, it's a dynamic system, and the output of the PLL will vary as well the output of the PID block. So it's confusing. But thank you, as soon as the PID works, I can work on it more.

3. Sorry again. I was describing the Properties window of the PLL block. So I was talking about the high and low limits (32767 and -32678 respectively). 

In fact, I've changed the values of the setpoint and the limits (5/10/100 and +-99999 respectively), and regardless of the setpoint and Sampling time, the PID output is 98304. And I see that the value of x*y increases (as the PID input), but the output has not changed. So it makes the operation of the PID even more confusing for me.

4. Yeah, the reason is that when this VI is opened via my FPGA project/FPGA target, I don't have the Control and Simulink function palette, so that PID is the only option.

5. Fair enough, thank you  But since the output of the PID is zero, I can't check so far, does this solution works or not in my application. 

Appreciate your time, thank you!