Transfer large data from FPGA to RT

[gmoogsta]

Hi there,
I'm using LV8.5 with PXI-8106 in a PXI-1042Q chassis and PXI-7813R rIO with 4 expansion chassis cRIO-9151, including several data-io modules. I've already read several documents what are the best techniques for transferring data from fpga to a RT-application but I found nothing that fits my requirements precisely.
I have to record approximately 15-20 different signals @1-10kHz in my RT-application, which are mostely acquired by my fpga-hardware (only a few by serial-port or non-fpga-can-card). My time critical loop in my RT-application runs with 25ms, the data-writing in a tdms-file should happen in the normal-priority-loop of the rt-application.
In my opinion, the amount of data I have to pass is quite high, if I estimate the amount based on 20 different signals with the acquisition-cycle about 250times shorter than my tcl runs...
Should I create for every channel a seperate FPGA-Fifo, distributed on the three available DMA-channels and transfer read the continous data in my TCL with simple polling (without interrupts)?! I see no way of bundling the data, apart from transferring data in clusters by indicators, which wouldn't be very efficient...
Can anyone make any suggestions how to handle the transferring-problem efficiently??

Thanks so far!

[Elmar_NI]

Hello Gmoogsta,

the best way is to use one DMA channel for each c Series modul (if possible).
And combine the data per array to the DMA channel.
You can find more info about that under the link below.

http://zone.ni.com/devzone/cda/tut/p/id/4534

Kind regards,

Elmar

[gmoogsta]

Hi Elmar,
thanks for your reply... This helps a lot 🙂

Unfortunately I've got 4 extension chassis with 3-4 additional modules in every single chassis, so I can't use seperate DMA-channels for every extension chassis... I'll see how good everything works... Thanks so far!

[Brian_R]

Hey Gmoogsta - I am currently writing example code for a customer who is trying to do what you are doing.  He has 4 cRIO-9151s and is doing 60 channels at 50 kS/s.  I proved the code in Windows on a Core 2 Duo.  I see you're using RT, but I think these suggestions are still relevant. 

1.  Use "Build Array.vi" and a "for" loop to write approximately 1/3 of your samples to each DMA FIFO in your FPGA VI.  It doesn't matter if it is exactly one third since the bus bandwidth is aggregate.  In my code, I have 48 channels on one FIFO, 8 on another, and 4 on the third.  These are broken down by the number of channels of each module type. 

2.  On the host VI, I have a producer loop that is waiting for interrupts from the FPGA.  I have configured the FIFO depth to be extremely deep on the host side.  I read at 25 kS/ch/read.  These are queued up in three separate queues - one for each DMA channel. 

3.  There are 3 consumer loops - one for each queue.  Use the "Decimate 1D Array.vi" to break up the massive arrays into each channel. 

Hope this helps!

-Brian

[gmoogsta]

Hi Brian,
thanks for your informationfilled, concrete answer... This will definitely help. Actually I didn't know the the DMA-channel-bandwith is aggregate. I thought it would be better to divide the channelcount quite equal on the DMA-channels... This makes it quite easier... Thank you!

[Brian_R]

The code is here:

Using the NI cRIO-9151 With High Channel Count Applications